diff --git a/Android.mk b/Android.mk
index 03bbde8..0f40b4f 100644
--- a/Android.mk
+++ b/Android.mk
@@ -92,7 +92,7 @@ $(eval $(call define-redroid-prebuilt-lib,libgallium_drv_video,,dri/libgallium_d
 
 
 ## amdgpu.ids
-#$(eval $(call define-redroid-prebuilt-etc,amdgpu.ids_p,amdgpu.ids,amdgpu.ids,hwdata))
+$(eval $(call define-redroid-prebuilt-etc,amdgpu.ids.redroid,,libdrm/amdgpu.ids,hwdata))
 
 
 # libs with SOVERSION
diff --git a/prebuilts.mk b/prebuilts.mk
index 0bc2b92..871f80b 100644
--- a/prebuilts.mk
+++ b/prebuilts.mk
@@ -1,4 +1,5 @@
 PRODUCT_PACKAGES += \
+    amdgpu.ids.redroid \
     libEGL_mesa \
     libGLESv1_CM_mesa \
     libGLESv2_mesa \
@@ -9,7 +10,3 @@ PRODUCT_PACKAGES += \
     vainfo \
     ffmpeg \
     ffprobe \
-
-# from AOSP
-PRODUCT_PACKAGES += \
-    amdgpu.ids \
diff --git a/prebuilts/aarch64/include/libdrm/nouveau/nouveau.h b/prebuilts/aarch64/include/libdrm/nouveau/nouveau.h
index 335ce77..0c632fe 100644
--- a/prebuilts/aarch64/include/libdrm/nouveau/nouveau.h
+++ b/prebuilts/aarch64/include/libdrm/nouveau/nouveau.h
@@ -273,4 +273,8 @@ struct nv04_notify {
 	uint32_t offset;
 	uint32_t length;
 };
+
+bool
+nouveau_check_dead_channel(struct nouveau_drm *, struct nouveau_object *chan);
+
 #endif
diff --git a/prebuilts/aarch64/include/libdrm/tegra_drm.h b/prebuilts/aarch64/include/libdrm/tegra_drm.h
index 6c07919..94cfc30 100644
--- a/prebuilts/aarch64/include/libdrm/tegra_drm.h
+++ b/prebuilts/aarch64/include/libdrm/tegra_drm.h
@@ -1,27 +1,8 @@
-/*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+/* SPDX-License-Identifier: MIT */
+/* Copyright (c) 2012-2020 NVIDIA Corporation */
 
-#ifndef _TEGRA_DRM_H_
-#define _TEGRA_DRM_H_
+#ifndef _UAPI_TEGRA_DRM_H_
+#define _UAPI_TEGRA_DRM_H_
 
 #include "drm.h"
 
@@ -29,6 +10,8 @@
 extern "C" {
 #endif
 
+/* Tegra DRM legacy UAPI. Only enabled with STAGING */
+
 #define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
 #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
 
@@ -649,8 +632,8 @@ struct drm_tegra_gem_get_flags {
 #define DRM_TEGRA_SYNCPT_READ		0x02
 #define DRM_TEGRA_SYNCPT_INCR		0x03
 #define DRM_TEGRA_SYNCPT_WAIT		0x04
-#define DRM_TEGRA_OPEN_CHANNEL		0x05
-#define DRM_TEGRA_CLOSE_CHANNEL		0x06
+#define DRM_TEGRA_OPEN_CHANNEL	        0x05
+#define DRM_TEGRA_CLOSE_CHANNEL	        0x06
 #define DRM_TEGRA_GET_SYNCPT		0x07
 #define DRM_TEGRA_SUBMIT		0x08
 #define DRM_TEGRA_GET_SYNCPT_BASE	0x09
@@ -674,6 +657,402 @@ struct drm_tegra_gem_get_flags {
 #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
 #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
 
+/* New Tegra DRM UAPI */
+
+/*
+ * Reported by the driver in the `capabilities` field.
+ *
+ * DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent
+ * with regard to the system memory.
+ */
+#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0)
+
+struct drm_tegra_channel_open {
+	/**
+	 * @host1x_class: [in]
+	 *
+	 * Host1x class of the engine that will be programmed using this
+	 * channel.
+	 */
+	__u32 host1x_class;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @context: [out]
+	 *
+	 * Opaque identifier corresponding to the opened channel.
+	 */
+	__u32 context;
+
+	/**
+	 * @version: [out]
+	 *
+	 * Version of the engine hardware. This can be used by userspace
+	 * to determine how the engine needs to be programmed.
+	 */
+	__u32 version;
+
+	/**
+	 * @capabilities: [out]
+	 *
+	 * Flags describing the hardware capabilities.
+	 */
+	__u32 capabilities;
+	__u32 padding;
+};
+
+struct drm_tegra_channel_close {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to close.
+	 */
+	__u32 context;
+	__u32 padding;
+};
+
+/*
+ * Mapping flags that can be used to influence how the mapping is created.
+ *
+ * DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access
+ * DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access
+ */
+#define DRM_TEGRA_CHANNEL_MAP_READ  (1 << 0)
+#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1)
+#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | \
+					  DRM_TEGRA_CHANNEL_MAP_WRITE)
+
+struct drm_tegra_channel_map {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to which make memory available for.
+	 */
+	__u32 context;
+
+	/**
+	 * @handle: [in]
+	 *
+	 * GEM handle of the memory to map.
+	 */
+	__u32 handle;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @mapping: [out]
+	 *
+	 * Identifier corresponding to the mapping, to be used for
+	 * relocations or unmapping later.
+	 */
+	__u32 mapping;
+};
+
+struct drm_tegra_channel_unmap {
+	/**
+	 * @context: [in]
+	 *
+	 * Channel identifier of the channel to unmap memory from.
+	 */
+	__u32 context;
+
+	/**
+	 * @mapping: [in]
+	 *
+	 * Mapping identifier of the memory mapping to unmap.
+	 */
+	__u32 mapping;
+};
+
+/* Submission */
+
+/**
+ * Specify that bit 39 of the patched-in address should be set to switch
+ * swizzling between Tegra and non-Tegra sector layout on systems that store
+ * surfaces in system memory in non-Tegra sector layout.
+ */
+#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0)
+
+struct drm_tegra_submit_buf {
+	/**
+	 * @mapping: [in]
+	 *
+	 * Identifier of the mapping to use in the submission.
+	 */
+	__u32 mapping;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * Information for relocation patching.
+	 */
+	struct {
+		/**
+		 * @target_offset: [in]
+		 *
+		 * Offset from the start of the mapping of the data whose
+		 * address is to be patched into the gather.
+		 */
+		__u64 target_offset;
+
+		/**
+		 * @gather_offset_words: [in]
+		 *
+		 * Offset in words from the start of the gather data to
+		 * where the address should be patched into.
+		 */
+		__u32 gather_offset_words;
+
+		/**
+		 * @shift: [in]
+		 *
+		 * Number of bits the address should be shifted right before
+		 * patching in.
+		 */
+		__u32 shift;
+	} reloc;
+};
+
+/**
+ * Execute `words` words of Host1x opcodes specified in the `gather_data_ptr`
+ * buffer. Each GATHER_UPTR command uses successive words from the buffer.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR		0
+/**
+ * Wait for a syncpoint to reach a value before continuing with further
+ * commands.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT		1
+/**
+ * Wait for a syncpoint to reach a value before continuing with further
+ * commands. The threshold is calculated relative to the start of the job.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE	2
+
+struct drm_tegra_submit_cmd_gather_uptr {
+	__u32 words;
+	__u32 reserved[3];
+};
+
+struct drm_tegra_submit_cmd_wait_syncpt {
+	__u32 id;
+	__u32 value;
+	__u32 reserved[2];
+};
+
+struct drm_tegra_submit_cmd {
+	/**
+	 * @type: [in]
+	 *
+	 * Command type to execute. One of the DRM_TEGRA_SUBMIT_CMD*
+	 * defines.
+	 */
+	__u32 type;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	union {
+		struct drm_tegra_submit_cmd_gather_uptr gather_uptr;
+		struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt;
+		__u32 reserved[4];
+	};
+};
+
+struct drm_tegra_submit_syncpt {
+	/**
+	 * @id: [in]
+	 *
+	 * ID of the syncpoint that the job will increment.
+	 */
+	__u32 id;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @increments: [in]
+	 *
+	 * Number of times the job will increment this syncpoint.
+	 */
+	__u32 increments;
+
+	/**
+	 * @value: [out]
+	 *
+	 * Value the syncpoint will have once the job has completed all
+	 * its specified syncpoint increments.
+	 *
+	 * Note that the kernel may increment the syncpoint before or after
+	 * the job. These increments are not reflected in this field.
+	 *
+	 * If the job hangs or times out, not all of the increments may
+	 * get executed.
+	 */
+	__u32 value;
+};
+
+struct drm_tegra_channel_submit {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to submit this job to.
+	 */
+	__u32 context;
+
+	/**
+	 * @num_bufs: [in]
+	 *
+	 * Number of elements in the `bufs_ptr` array.
+	 */
+	__u32 num_bufs;
+
+	/**
+	 * @num_cmds: [in]
+	 *
+	 * Number of elements in the `cmds_ptr` array.
+	 */
+	__u32 num_cmds;
+
+	/**
+	 * @gather_data_words: [in]
+	 *
+	 * Number of 32-bit words in the `gather_data_ptr` array.
+	 */
+	__u32 gather_data_words;
+
+	/**
+	 * @bufs_ptr: [in]
+	 *
+	 * Pointer to an array of drm_tegra_submit_buf structures.
+	 */
+	__u64 bufs_ptr;
+
+	/**
+	 * @cmds_ptr: [in]
+	 *
+	 * Pointer to an array of drm_tegra_submit_cmd structures.
+	 */
+	__u64 cmds_ptr;
+
+	/**
+	 * @gather_data_ptr: [in]
+	 *
+	 * Pointer to an array of Host1x opcodes to be used by GATHER_UPTR
+	 * commands.
+	 */
+	__u64 gather_data_ptr;
+
+	/**
+	 * @syncobj_in: [in]
+	 *
+	 * Handle for DRM syncobj that will be waited before submission.
+	 * Ignored if zero.
+	 */
+	__u32 syncobj_in;
+
+	/**
+	 * @syncobj_out: [in]
+	 *
+	 * Handle for DRM syncobj that will have its fence replaced with
+	 * the job's completion fence. Ignored if zero.
+	 */
+	__u32 syncobj_out;
+
+	/**
+	 * @syncpt_incr: [in,out]
+	 *
+	 * Information about the syncpoint the job will increment.
+	 */
+	struct drm_tegra_submit_syncpt syncpt;
+};
+
+struct drm_tegra_syncpoint_allocate {
+	/**
+	 * @id: [out]
+	 *
+	 * ID of allocated syncpoint.
+	 */
+	__u32 id;
+	__u32 padding;
+};
+
+struct drm_tegra_syncpoint_free {
+	/**
+	 * @id: [in]
+	 *
+	 * ID of syncpoint to free.
+	 */
+	__u32 id;
+	__u32 padding;
+};
+
+struct drm_tegra_syncpoint_wait {
+	/**
+	 * @timeout: [in]
+	 *
+	 * Absolute timestamp at which the wait will time out.
+	 */
+	__s64 timeout_ns;
+
+	/**
+	 * @id: [in]
+	 *
+	 * ID of syncpoint to wait on.
+	 */
+	__u32 id;
+
+	/**
+	 * @threshold: [in]
+	 *
+	 * Threshold to wait for.
+	 */
+	__u32 threshold;
+
+	/**
+	 * @value: [out]
+	 *
+	 * Value of the syncpoint upon wait completion.
+	 */
+	__u32 value;
+
+	__u32 padding;
+};
+
+#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open)
+#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close)
+#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map)
+#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap)
+#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit)
+
+#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate)
+#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free)
+#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait)
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/prebuilts/aarch64/include/xf86drmMode.h b/prebuilts/aarch64/include/xf86drmMode.h
index 19bf91d..4617d1e 100644
--- a/prebuilts/aarch64/include/xf86drmMode.h
+++ b/prebuilts/aarch64/include/xf86drmMode.h
@@ -380,6 +380,19 @@ extern drmModeConnectorPtr drmModeGetConnector(int fd,
 extern drmModeConnectorPtr drmModeGetConnectorCurrent(int fd,
 						      uint32_t connector_id);
 
+/**
+ * Get a bitmask of CRTCs a connector is compatible with.
+ *
+ * The bits reference CRTC indices. If the n-th CRTC is compatible with the
+ * connector, the n-th bit will be set. The indices are taken from the array
+ * returned by drmModeGetResources(). The indices are different from the object
+ * IDs.
+ *
+ * Zero is returned on error.
+ */
+extern uint32_t drmModeConnectorGetPossibleCrtcs(int fd,
+                                                 const drmModeConnector *connector);
+
 /**
  * Attaches the given mode to an connector.
  */
@@ -433,18 +446,18 @@ extern int drmModeObjectSetProperty(int fd, uint32_t object_id,
 typedef struct _drmModeAtomicReq drmModeAtomicReq, *drmModeAtomicReqPtr;
 
 extern drmModeAtomicReqPtr drmModeAtomicAlloc(void);
-extern drmModeAtomicReqPtr drmModeAtomicDuplicate(drmModeAtomicReqPtr req);
+extern drmModeAtomicReqPtr drmModeAtomicDuplicate(const drmModeAtomicReqPtr req);
 extern int drmModeAtomicMerge(drmModeAtomicReqPtr base,
-			      drmModeAtomicReqPtr augment);
+			      const drmModeAtomicReqPtr augment);
 extern void drmModeAtomicFree(drmModeAtomicReqPtr req);
-extern int drmModeAtomicGetCursor(drmModeAtomicReqPtr req);
+extern int drmModeAtomicGetCursor(const drmModeAtomicReqPtr req);
 extern void drmModeAtomicSetCursor(drmModeAtomicReqPtr req, int cursor);
 extern int drmModeAtomicAddProperty(drmModeAtomicReqPtr req,
 				    uint32_t object_id,
 				    uint32_t property_id,
 				    uint64_t value);
 extern int drmModeAtomicCommit(int fd,
-			       drmModeAtomicReqPtr req,
+			       const drmModeAtomicReqPtr req,
 			       uint32_t flags,
 			       void *user_data);
 
@@ -475,6 +488,15 @@ extern drmModeObjectListPtr drmModeGetLease(int fd);
 
 extern int drmModeRevokeLease(int fd, uint32_t lessee_id);
 
+/**
+ * Get a string describing a connector type.
+ *
+ * NULL is returned if the connector type is unsupported. Callers should handle
+ * this gracefully, e.g. by falling back to "Unknown" or printing the raw value.
+ */
+extern const char *
+drmModeGetConnectorTypeName(uint32_t connector_type);
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/prebuilts/aarch64/lib/libdrm.so.2.4.0 b/prebuilts/aarch64/lib/libdrm.so.2.4.0
index d53cc36..82779e3 100755
Binary files a/prebuilts/aarch64/lib/libdrm.so.2.4.0 and b/prebuilts/aarch64/lib/libdrm.so.2.4.0 differ
diff --git a/prebuilts/aarch64/lib/libdrm_amdgpu.so.1.0.0 b/prebuilts/aarch64/lib/libdrm_amdgpu.so.1.0.0
index 8d369e0..e59e654 100755
Binary files a/prebuilts/aarch64/lib/libdrm_amdgpu.so.1.0.0 and b/prebuilts/aarch64/lib/libdrm_amdgpu.so.1.0.0 differ
diff --git a/prebuilts/aarch64/lib/libdrm_nouveau.so.2.0.0 b/prebuilts/aarch64/lib/libdrm_nouveau.so.2.0.0
index c330668..70010ae 100755
Binary files a/prebuilts/aarch64/lib/libdrm_nouveau.so.2.0.0 and b/prebuilts/aarch64/lib/libdrm_nouveau.so.2.0.0 differ
diff --git a/prebuilts/aarch64/share/amdgpu.ids b/prebuilts/aarch64/share/amdgpu.ids
deleted file mode 100644
index 0040a38..0000000
--- a/prebuilts/aarch64/share/amdgpu.ids
+++ /dev/null
@@ -1,300 +0,0 @@
-# List of AMDGPU IDs
-#
-# Syntax:
-# device_id,	revision_id,	product_name        <-- single tab after comma
-
-1.0.0
-15DD,	C3,	AMD Radeon Vega 3 Graphics
-15DD,	CB,	AMD Radeon Vega 3 Graphics
-15DD,	CE,	AMD Radeon Vega 3 Graphics
-15DD,	D8,	AMD Radeon Vega 3 Graphics
-15DD,	CC,	AMD Radeon Vega 6 Graphics
-15DD,	D9,	AMD Radeon Vega 6 Graphics
-15DD,	C2,	AMD Radeon Vega 8 Graphics
-15DD,	C4,	AMD Radeon Vega 8 Graphics
-15DD,	C8,	AMD Radeon Vega 8 Graphics
-15DD,	CA,	AMD Radeon Vega 8 Graphics
-15DD,	D1,	AMD Radeon Vega 8 Graphics
-15DD,	D5,	AMD Radeon Vega 8 Graphics
-15DD,	D7,	AMD Radeon Vega 8 Graphics
-15DD,	C3,	AMD Radeon Vega 10 Graphics
-15DD,	D0,	AMD Radeon Vega 10 Graphics
-15DD,	C1,	AMD Radeon Vega 11 Graphics
-15DD,	C6,	AMD Radeon Vega 11 Graphics
-15DD,	C9,	AMD Radeon Vega 11 Graphics
-15DD,	D3,	AMD Radeon Vega 11 Graphics
-15DD,	D6,	AMD Radeon Vega 11 Graphics
-15DD,	81,	AMD Ryzen Embedded V1807B with Radeon Vega Gfx
-15DD,	82,	AMD Ryzen Embedded V1756B with Radeon Vega Gfx
-15DD,	83,	AMD Ryzen Embedded V1605B with Radeon Vega Gfx
-15DD,	85,	AMD Ryzen Embedded V1202B with Radeon Vega Gfx
-15D8,	93,	AMD Radeon Vega 1 Graphics
-15D8,	C4,	AMD Radeon Vega 3 Graphics
-15D8,	C5,	AMD Radeon Vega 3 Graphics
-15D8,	CC,	AMD Radeon Vega 3 Graphics
-15D8,	CE,	AMD Radeon Vega 3 Graphics
-15D8,	CF,	AMD Radeon Vega 3 Graphics
-15D8,	D4,	AMD Radeon Vega 3 Graphics
-15D8,	DC,	AMD Radeon Vega 3 Graphics
-15D8,	DD,	AMD Radeon Vega 3 Graphics
-15D8,	DE,	AMD Radeon Vega 3 Graphics
-15D8,	DF,	AMD Radeon Vega 3 Graphics
-15D8,	E3,	AMD Radeon Vega 3 Graphics
-15D8,	E4,	AMD Radeon Vega 3 Graphics
-15D8,	A3,	AMD Radeon Vega 6 Graphics
-15D8,	B3,	AMD Radeon Vega 6 Graphics
-15D8,	C3,	AMD Radeon Vega 6 Graphics
-15D8,	D3,	AMD Radeon Vega 6 Graphics
-15D8,	A2,	AMD Radeon Vega 8 Graphics
-15D8,	B2,	AMD Radeon Vega 8 Graphics
-15D8,	C2,	AMD Radeon Vega 8 Graphics
-15D8,	C9,	AMD Radeon Vega 8 Graphics
-15D8,	CB,	AMD Radeon Vega 8 Graphics
-15D8,	D2,	AMD Radeon Vega 8 Graphics
-15D8,	D9,	AMD Radeon Vega 8 Graphics
-15D8,	DB,	AMD Radeon Vega 8 Graphics
-15D8,	A1,	AMD Radeon Vega 10 Graphics
-15D8,	B1,	AMD Radeon Vega 10 Graphics
-15D8,	C1,	AMD Radeon Vega 10 Graphics
-15D8,	D1,	AMD Radeon Vega 10 Graphics
-15D8,	C8,	AMD Radeon Vega 11 Graphics
-15D8,	CA,	AMD Radeon Vega 11 Graphics
-15D8,	D8,	AMD Radeon Vega 11 Graphics
-15D8,	DA,	AMD Radeon Vega 11 Graphics
-15D8,	91,	AMD Ryzen Embedded R1606G with Radeon Vega Gfx
-15D8,	92,	AMD Ryzen Embedded R1505G with Radeon Vega Gfx
-15D8,	CF,	AMD Ryzen Embedded R1305G with Radeon Vega Gfx
-15D8,	E4,	AMD Ryzen Embedded R1102G with Radeon Vega Gfx
-163F,	AE,	AMD Custom GPU 0405
-6600,	0,	AMD Radeon HD 8600 / 8700M
-6600,	81,	AMD Radeon R7 M370
-6601,	0,	AMD Radeon HD 8500M / 8700M
-6604,	0,	AMD Radeon R7 M265 Series
-6604,	81,	AMD Radeon R7 M350
-6605,	0,	AMD Radeon R7 M260 Series
-6605,	81,	AMD Radeon R7 M340
-6606,	0,	AMD Radeon HD 8790M
-6607,	0,	AMD Radeon HD 8530M
-6608,	0,	AMD FirePro W2100
-6610,	0,	AMD Radeon HD 8600 Series
-6610,	81,	AMD Radeon R7 350
-6610,	83,	AMD Radeon R5 340
-6611,	0,	AMD Radeon HD 8500 Series
-6613,	0,	AMD Radeon HD 8500 series
-6617,	C7,	AMD Radeon R7 240 Series
-6640,	0,	AMD Radeon HD 8950
-6640,	80,	AMD Radeon R9 M380
-6646,	0,	AMD Radeon R9 M280X
-6646,	80,	AMD Radeon R9 M470X
-6647,	0,	AMD Radeon R9 M270X
-6647,	80,	AMD Radeon R9 M380
-6649,	0,	AMD FirePro W5100
-6658,	0,	AMD Radeon R7 200 Series
-665C,	0,	AMD Radeon HD 7700 Series
-665D,	0,	AMD Radeon R7 200 Series
-665F,	81,	AMD Radeon R7 300 Series
-6660,	0,	AMD Radeon HD 8600M Series
-6660,	81,	AMD Radeon R5 M335
-6660,	83,	AMD Radeon R5 M330
-6663,	0,	AMD Radeon HD 8500M Series
-6663,	83,	AMD Radeon R5 M320
-6664,	0,	AMD Radeon R5 M200 Series
-6665,	0,	AMD Radeon R5 M200 Series
-6665,	83,	AMD Radeon R5 M320
-6667,	0,	AMD Radeon R5 M200 Series
-666F,	0,	AMD Radeon HD 8500M
-66A1,	06,	AMD Radeon Pro VII
-66AF,	C1,	AMD Radeon VII
-6780,	0,	ATI FirePro V (FireGL V) Graphics Adapter
-678A,	0,	ATI FirePro V (FireGL V) Graphics Adapter
-6798,	0,	AMD Radeon HD 7900 Series
-679A,	0,	AMD Radeon HD 7900 Series
-679B,	0,	AMD Radeon HD 7900 Series
-679E,	0,	AMD Radeon HD 7800 Series
-67A0,	0,	AMD Radeon FirePro W9100
-67A1,	0,	AMD Radeon FirePro W8100
-67B0,	0,	AMD Radeon R9 200 Series
-67B0,	80,	AMD Radeon R9 390 Series
-67B1,	0,	AMD Radeon R9 200 Series
-67B1,	80,	AMD Radeon R9 390 Series
-67B9,	0,	AMD Radeon R9 200 Series
-67DF,	C1,	AMD Radeon RX 580 Series
-67DF,	C2,	AMD Radeon RX 570 Series
-67DF,	C3,	AMD Radeon RX 580 Series
-67DF,	C4,	AMD Radeon RX 480 Graphics
-67DF,	C5,	AMD Radeon RX 470 Graphics
-67DF,	C6,	AMD Radeon RX 570 Series
-67DF,	C7,	AMD Radeon RX 480 Graphics
-67DF,	CF,	AMD Radeon RX 470 Graphics
-67DF,	D7,	AMD Radeon RX 470 Graphics
-67DF,	E0,	AMD Radeon RX 470 Series
-67DF,	E1,	AMD Radeon RX 590 Series
-67DF,	E3,	AMD Radeon RX Series
-67DF,	E7,	AMD Radeon RX 580 Series
-67DF,	EF,	AMD Radeon RX 570 Series
-67DF,	F7,	AMD Radeon RX P30PH
-67C2,	01,	AMD Radeon Pro V7350x2
-67C2,	02,	AMD Radeon Pro V7300X
-67C4,	00,	AMD Radeon Pro WX 7100 Graphics
-67C4,	80,	AMD Radeon E9560 / E9565 Graphics
-67C7,	00,	AMD Radeon Pro WX 5100 Graphics
-67C7,	80,	AMD Radeon E9390 Graphics
-67C0,	00,	AMD Radeon Pro WX 7100 Graphics
-67D0,	01,	AMD Radeon Pro V7350x2
-67D0,	02,	AMD Radeon Pro V7300X
-67E0,	00,	AMD Radeon Pro WX Series
-67E3,	00,	AMD Radeon Pro WX 4100
-67E8,	00,	AMD Radeon Pro WX Series
-67E8,	01,	AMD Radeon Pro WX Series
-67E8,	80,	AMD Radeon E9260 Graphics
-67EB,	00,	AMD Radeon Pro V5300X
-67EF,	C0,	AMD Radeon RX Graphics
-67EF,	C1,	AMD Radeon RX 460 Graphics
-67EF,	C3,	AMD Radeon RX Series
-67EF,	C5,	AMD Radeon RX 460 Graphics
-67EF,	C7,	AMD Radeon RX Graphics
-67EF,	CF,	AMD Radeon RX 460 Graphics
-67EF,	E2,	AMD Radeon RX 560X
-67EF,	E0,	AMD Radeon RX 560 Series
-67EF,	E1,	AMD Radeon RX Series
-67EF,	E3,	AMD Radeon RX Series
-67EF,	E5,	AMD Radeon RX 560 Series
-67EF,	EF,	AMD Radeon RX Graphics
-67EF,	FF,	AMD Radeon RX 460 Graphics
-67FF,	C0,	AMD Radeon RX Graphics
-67FF,	C1,	AMD Radeon RX Graphics
-67FF,	CF,	AMD Radeon RX 560 Series
-67FF,	EF,	AMD Radeon RX 560 Series
-67FF,	FF,	AMD Radeon RX 550 Series
-6800,	0,	AMD Radeon HD 7970M
-6801,	0,	AMD Radeon HD 8970M
-6808,	0,	ATI FirePro V(FireGL V) Graphics Adapter
-6809,	0,	ATI FirePro V(FireGL V) Graphics Adapter
-6810,	0,	AMD Radeon HD 8800 Series
-6810,	81,	AMD Radeon R7 370 Series
-6811,	0,	AMD Radeon HD 8800 Series
-6811,	81,	AMD Radeon R7 300 Series
-6818,	0,	AMD Radeon HD 7800 Series
-6819,	0,	AMD Radeon HD 7800 Series
-6820,	0,	AMD Radeon HD 8800M Series
-6820,	81,	AMD Radeon R9 M375
-6820,	83,	AMD Radeon R9 M375X
-6821,	0,	AMD Radeon HD 8800M Series
-6821,	87,	AMD Radeon R7 M380
-6821,	83,	AMD Radeon R9 M370X
-6822,	0,	AMD Radeon E8860
-6823,	0,	AMD Radeon HD 8800M Series
-6825,	0,	AMD Radeon HD 7800M Series
-6827,	0,	AMD Radeon HD 7800M Series
-6828,	0,	ATI FirePro V(FireGL V) Graphics Adapter
-682B,	0,	AMD Radeon HD 8800M Series
-682B,	87,	AMD Radeon R9 M360
-682C,	0,	AMD FirePro W4100
-682D,	0,	AMD Radeon HD 7700M Series
-682F,	0,	AMD Radeon HD 7700M Series
-6835,	0,	AMD Radeon R7 Series / HD 9000 Series
-6837,	0,	AMD Radeon HD 7700 Series
-683D,	0,	AMD Radeon HD 7700 Series
-683F,	0,	AMD Radeon HD 7700 Series
-6860,	00,	AMD Radeon Instinct MI25
-6860,	01,	AMD Radeon Instinct MI25
-6860,	02,	AMD Radeon Instinct MI25
-6860,	03,	AMD Radeon Pro V340
-6860,	04,	AMD Radeon Instinct MI25x2
-6860,	07,	AMD Radeon Pro V320
-6861,	00,	AMD Radeon Pro WX 9100
-6862,	00,	AMD Radeon Pro SSG
-6863,	00,	AMD Radeon Vega Frontier Edition
-6864,	03,	AMD Radeon Pro V340
-6864,	04,	AMD Radeon Instinct MI25x2
-6868,	00,	AMD Radeon Pro WX 8200
-686C,	00,	AMD Radeon Instinct MI25 MxGPU
-686C,	01,	AMD Radeon Instinct MI25 MxGPU
-686C,	02,	AMD Radeon Instinct MI25 MxGPU
-686C,	03,	AMD Radeon Pro V340 MxGPU
-686C,	04,	AMD Radeon Instinct MI25x2 MxGPU
-686C,	05,	AMD Radeon Pro V340L MxGPU
-686C,	06,	AMD Radeon Instinct MI25 MxGPU
-687F,	C0,	AMD Radeon RX Vega
-687F,	C1,	AMD Radeon RX Vega
-687F,	C3,	AMD Radeon RX Vega
-6900,	0,	AMD Radeon R7 M260
-6900,	81,	AMD Radeon R7 M360
-6900,	83,	AMD Radeon R7 M340
-6901,	0,	AMD Radeon R5 M255
-6907,	0,	AMD Radeon R5 M255
-6907,	87,	AMD Radeon R5 M315
-6920,	0,	AMD Radeon R9 M395X
-6920,	1,	AMD Radeon R9 M390X
-6921,	0,	AMD Radeon R9 M295X
-6929,	0,	AMD FirePro S7150
-692B,	0,	AMD FirePro W7100
-6938,	0,	AMD Radeon R9 200 Series
-6938,	F0,	AMD Radeon R9 200 Series
-6938,	F1,	AMD Radeon R9 380 Series
-6939,	F0,	AMD Radeon R9 200 Series
-6939,	0,	AMD Radeon R9 200 Series
-6939,	F1,	AMD Radeon R9 380 Series
-6980,	00,	AMD Radeon Pro WX 3100
-6981,	00,	AMD Radeon Pro WX 3200 Series
-6981,	01,	AMD Radeon Pro WX 3200 Series
-6981,	10,	AMD Radeon Pro WX 3200 Series
-6985,	00,	AMD Radeon Pro WX 3100
-6987,	80,	AMD Embedded Radeon E9171
-6987,	C0,	AMD Radeon 550X Series
-6987,	C1,	AMD Radeon RX 640
-6987,	C3,	AMD Radeon 540X Series
-6995,	00,	AMD Radeon Pro WX 2100
-6997,	00,	AMD Radeon Pro WX 2100
-699F,	81,	AMD Embedded Radeon E9170 Series
-699F,	C0,	AMD Radeon 500 Series
-699F,	C1,	AMD Radeon 540 Series
-699F,	C3,	AMD Radeon 500 Series
-699F,	C7,	AMD Radeon RX 550 / 550 Series
-7300,	C1,	AMD FirePro S9300 x2
-7300,	C8,	AMD Radeon R9 Fury Series
-7300,	C9,	AMD Radeon Pro Duo
-7300,	CB,	AMD Radeon R9 Fury Series
-7300,	CA,	AMD Radeon R9 Fury Series
-7312,	00,	AMD Radeon Pro W5700
-731E,	C6,	AMD Radeon RX 5700XTB
-731E,	C7,	AMD Radeon RX 5700B
-731F,	C0,	AMD Radeon RX 5700 XT 50th Anniversary
-731F,	C1,	AMD Radeon RX 5700 XT
-731F,	C2,	AMD Radeon RX 5600M
-731F,	C3,	AMD Radeon RX 5700M
-731F,	C4,	AMD Radeon RX 5700
-731F,	C5,	AMD Radeon RX 5700 XT
-731F,	CA,	AMD Radeon RX 5600 XT
-731F,	CB,	AMD Radeon RX 5600 OEM
-7340,	C1,	AMD Radeon RX 5500M
-7340,	C5,	AMD Radeon RX 5500 XT
-7340,	C7,	AMD Radeon RX 5500
-7340,	C9,	AMD Radeon RX 5500XTB
-7340,	CF,	AMD Radeon RX 5300
-7341,	00,	AMD Radeon Pro W5500
-7347,	00,	AMD Radeon Pro W5500M
-73A3,	00,	AMD Radeon Pro W6800
-73AF,	C0,	AMD Radeon RX 6900 XT
-73BF,	C0,	AMD Radeon RX 6900 XT
-73BF,	C1,	AMD Radeon RX 6800 XT
-73BF,	C3,	AMD Radeon RX 6800
-73DF,	C1,	AMD Radeon RX 6700 XT
-73DF,	C3,	AMD Radeon RX 6800M
-73DF,	C5,	AMD Radeon RX 6700 XT
-73DF,	CF,	AMD Radeon RX 6700M
-73E1,	00,	AMD Radeon Pro W6600M
-73E3,	00,	AMD Radeon Pro W6600
-73FF,	C1,	AMD Radeon RX 6600 XT
-73FF,	C3,	AMD Radeon RX 6600M
-9874,	C4,	AMD Radeon R7 Graphics
-9874,	C5,	AMD Radeon R6 Graphics
-9874,	C6,	AMD Radeon R6 Graphics
-9874,	C7,	AMD Radeon R5 Graphics
-9874,	C8,	AMD Radeon R7 Graphics
-9874,	81,	AMD Radeon R6 Graphics
-9874,	87,	AMD Radeon R5 Graphics
-9874,	85,	AMD Radeon R6 Graphics
-9874,	84,	AMD Radeon R7 Graphics
-6FDF,	E7,	AMD Radeon RX 590 GME
-6FDF,	EF,	AMD Radeon RX 580 2048SP
diff --git a/prebuilts/aarch64/share/libdrm/amdgpu.ids b/prebuilts/aarch64/share/libdrm/amdgpu.ids
index 0040a38..0d2b884 100644
--- a/prebuilts/aarch64/share/libdrm/amdgpu.ids
+++ b/prebuilts/aarch64/share/libdrm/amdgpu.ids
@@ -275,18 +275,35 @@
 7341,	00,	AMD Radeon Pro W5500
 7347,	00,	AMD Radeon Pro W5500M
 73A3,	00,	AMD Radeon Pro W6800
+73A5,	C0,	AMD Radeon RX 6950 XT
 73AF,	C0,	AMD Radeon RX 6900 XT
 73BF,	C0,	AMD Radeon RX 6900 XT
 73BF,	C1,	AMD Radeon RX 6800 XT
 73BF,	C3,	AMD Radeon RX 6800
+73DF,	C0,	AMD Radeon RX 6750 XT
 73DF,	C1,	AMD Radeon RX 6700 XT
 73DF,	C3,	AMD Radeon RX 6800M
 73DF,	C5,	AMD Radeon RX 6700 XT
 73DF,	CF,	AMD Radeon RX 6700M
 73E1,	00,	AMD Radeon Pro W6600M
 73E3,	00,	AMD Radeon Pro W6600
+73EF,	C0,	AMD Radeon RX 6800S
+73EF,	C1,	AMD Radeon RX 6650 XT
+73EF,	C2,	AMD Radeon RX 6700S
+73EF,	C3,	AMD Radeon RX 6650M
+73EF,	C4,	AMD Radeon RX 6650M XT
 73FF,	C1,	AMD Radeon RX 6600 XT
 73FF,	C3,	AMD Radeon RX 6600M
+73FF,	C7,	AMD Radeon RX 6600
+73FF,	CB,	AMD Radeon RX 6600S
+7421,	00,	AMD Radeon Pro W6500M
+7422,	00,	AMD Radeon PRO W6400
+7423,	00,	AMD Radeon Pro W6300M
+7424,	00,	AMD Radeon RX 6300
+743F,	C1,	AMD Radeon RX 6500 XT
+743F,	C3,	AMD Radeon RX 6500
+743F,	C7,	AMD Radeon RX 6400
+743F,	CF,	AMD Radeon RX 6300M
 9874,	C4,	AMD Radeon R7 Graphics
 9874,	C5,	AMD Radeon R6 Graphics
 9874,	C6,	AMD Radeon R6 Graphics
diff --git a/prebuilts/arm/include/libdrm/nouveau/nouveau.h b/prebuilts/arm/include/libdrm/nouveau/nouveau.h
index 335ce77..0c632fe 100644
--- a/prebuilts/arm/include/libdrm/nouveau/nouveau.h
+++ b/prebuilts/arm/include/libdrm/nouveau/nouveau.h
@@ -273,4 +273,8 @@ struct nv04_notify {
 	uint32_t offset;
 	uint32_t length;
 };
+
+bool
+nouveau_check_dead_channel(struct nouveau_drm *, struct nouveau_object *chan);
+
 #endif
diff --git a/prebuilts/arm/include/libdrm/tegra_drm.h b/prebuilts/arm/include/libdrm/tegra_drm.h
index 6c07919..94cfc30 100644
--- a/prebuilts/arm/include/libdrm/tegra_drm.h
+++ b/prebuilts/arm/include/libdrm/tegra_drm.h
@@ -1,27 +1,8 @@
-/*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+/* SPDX-License-Identifier: MIT */
+/* Copyright (c) 2012-2020 NVIDIA Corporation */
 
-#ifndef _TEGRA_DRM_H_
-#define _TEGRA_DRM_H_
+#ifndef _UAPI_TEGRA_DRM_H_
+#define _UAPI_TEGRA_DRM_H_
 
 #include "drm.h"
 
@@ -29,6 +10,8 @@
 extern "C" {
 #endif
 
+/* Tegra DRM legacy UAPI. Only enabled with STAGING */
+
 #define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
 #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
 
@@ -649,8 +632,8 @@ struct drm_tegra_gem_get_flags {
 #define DRM_TEGRA_SYNCPT_READ		0x02
 #define DRM_TEGRA_SYNCPT_INCR		0x03
 #define DRM_TEGRA_SYNCPT_WAIT		0x04
-#define DRM_TEGRA_OPEN_CHANNEL		0x05
-#define DRM_TEGRA_CLOSE_CHANNEL		0x06
+#define DRM_TEGRA_OPEN_CHANNEL	        0x05
+#define DRM_TEGRA_CLOSE_CHANNEL	        0x06
 #define DRM_TEGRA_GET_SYNCPT		0x07
 #define DRM_TEGRA_SUBMIT		0x08
 #define DRM_TEGRA_GET_SYNCPT_BASE	0x09
@@ -674,6 +657,402 @@ struct drm_tegra_gem_get_flags {
 #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
 #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
 
+/* New Tegra DRM UAPI */
+
+/*
+ * Reported by the driver in the `capabilities` field.
+ *
+ * DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent
+ * with regard to the system memory.
+ */
+#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0)
+
+struct drm_tegra_channel_open {
+	/**
+	 * @host1x_class: [in]
+	 *
+	 * Host1x class of the engine that will be programmed using this
+	 * channel.
+	 */
+	__u32 host1x_class;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @context: [out]
+	 *
+	 * Opaque identifier corresponding to the opened channel.
+	 */
+	__u32 context;
+
+	/**
+	 * @version: [out]
+	 *
+	 * Version of the engine hardware. This can be used by userspace
+	 * to determine how the engine needs to be programmed.
+	 */
+	__u32 version;
+
+	/**
+	 * @capabilities: [out]
+	 *
+	 * Flags describing the hardware capabilities.
+	 */
+	__u32 capabilities;
+	__u32 padding;
+};
+
+struct drm_tegra_channel_close {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to close.
+	 */
+	__u32 context;
+	__u32 padding;
+};
+
+/*
+ * Mapping flags that can be used to influence how the mapping is created.
+ *
+ * DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access
+ * DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access
+ */
+#define DRM_TEGRA_CHANNEL_MAP_READ  (1 << 0)
+#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1)
+#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | \
+					  DRM_TEGRA_CHANNEL_MAP_WRITE)
+
+struct drm_tegra_channel_map {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to which make memory available for.
+	 */
+	__u32 context;
+
+	/**
+	 * @handle: [in]
+	 *
+	 * GEM handle of the memory to map.
+	 */
+	__u32 handle;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @mapping: [out]
+	 *
+	 * Identifier corresponding to the mapping, to be used for
+	 * relocations or unmapping later.
+	 */
+	__u32 mapping;
+};
+
+struct drm_tegra_channel_unmap {
+	/**
+	 * @context: [in]
+	 *
+	 * Channel identifier of the channel to unmap memory from.
+	 */
+	__u32 context;
+
+	/**
+	 * @mapping: [in]
+	 *
+	 * Mapping identifier of the memory mapping to unmap.
+	 */
+	__u32 mapping;
+};
+
+/* Submission */
+
+/**
+ * Specify that bit 39 of the patched-in address should be set to switch
+ * swizzling between Tegra and non-Tegra sector layout on systems that store
+ * surfaces in system memory in non-Tegra sector layout.
+ */
+#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0)
+
+struct drm_tegra_submit_buf {
+	/**
+	 * @mapping: [in]
+	 *
+	 * Identifier of the mapping to use in the submission.
+	 */
+	__u32 mapping;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * Information for relocation patching.
+	 */
+	struct {
+		/**
+		 * @target_offset: [in]
+		 *
+		 * Offset from the start of the mapping of the data whose
+		 * address is to be patched into the gather.
+		 */
+		__u64 target_offset;
+
+		/**
+		 * @gather_offset_words: [in]
+		 *
+		 * Offset in words from the start of the gather data to
+		 * where the address should be patched into.
+		 */
+		__u32 gather_offset_words;
+
+		/**
+		 * @shift: [in]
+		 *
+		 * Number of bits the address should be shifted right before
+		 * patching in.
+		 */
+		__u32 shift;
+	} reloc;
+};
+
+/**
+ * Execute `words` words of Host1x opcodes specified in the `gather_data_ptr`
+ * buffer. Each GATHER_UPTR command uses successive words from the buffer.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR		0
+/**
+ * Wait for a syncpoint to reach a value before continuing with further
+ * commands.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT		1
+/**
+ * Wait for a syncpoint to reach a value before continuing with further
+ * commands. The threshold is calculated relative to the start of the job.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE	2
+
+struct drm_tegra_submit_cmd_gather_uptr {
+	__u32 words;
+	__u32 reserved[3];
+};
+
+struct drm_tegra_submit_cmd_wait_syncpt {
+	__u32 id;
+	__u32 value;
+	__u32 reserved[2];
+};
+
+struct drm_tegra_submit_cmd {
+	/**
+	 * @type: [in]
+	 *
+	 * Command type to execute. One of the DRM_TEGRA_SUBMIT_CMD*
+	 * defines.
+	 */
+	__u32 type;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	union {
+		struct drm_tegra_submit_cmd_gather_uptr gather_uptr;
+		struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt;
+		__u32 reserved[4];
+	};
+};
+
+struct drm_tegra_submit_syncpt {
+	/**
+	 * @id: [in]
+	 *
+	 * ID of the syncpoint that the job will increment.
+	 */
+	__u32 id;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @increments: [in]
+	 *
+	 * Number of times the job will increment this syncpoint.
+	 */
+	__u32 increments;
+
+	/**
+	 * @value: [out]
+	 *
+	 * Value the syncpoint will have once the job has completed all
+	 * its specified syncpoint increments.
+	 *
+	 * Note that the kernel may increment the syncpoint before or after
+	 * the job. These increments are not reflected in this field.
+	 *
+	 * If the job hangs or times out, not all of the increments may
+	 * get executed.
+	 */
+	__u32 value;
+};
+
+struct drm_tegra_channel_submit {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to submit this job to.
+	 */
+	__u32 context;
+
+	/**
+	 * @num_bufs: [in]
+	 *
+	 * Number of elements in the `bufs_ptr` array.
+	 */
+	__u32 num_bufs;
+
+	/**
+	 * @num_cmds: [in]
+	 *
+	 * Number of elements in the `cmds_ptr` array.
+	 */
+	__u32 num_cmds;
+
+	/**
+	 * @gather_data_words: [in]
+	 *
+	 * Number of 32-bit words in the `gather_data_ptr` array.
+	 */
+	__u32 gather_data_words;
+
+	/**
+	 * @bufs_ptr: [in]
+	 *
+	 * Pointer to an array of drm_tegra_submit_buf structures.
+	 */
+	__u64 bufs_ptr;
+
+	/**
+	 * @cmds_ptr: [in]
+	 *
+	 * Pointer to an array of drm_tegra_submit_cmd structures.
+	 */
+	__u64 cmds_ptr;
+
+	/**
+	 * @gather_data_ptr: [in]
+	 *
+	 * Pointer to an array of Host1x opcodes to be used by GATHER_UPTR
+	 * commands.
+	 */
+	__u64 gather_data_ptr;
+
+	/**
+	 * @syncobj_in: [in]
+	 *
+	 * Handle for DRM syncobj that will be waited before submission.
+	 * Ignored if zero.
+	 */
+	__u32 syncobj_in;
+
+	/**
+	 * @syncobj_out: [in]
+	 *
+	 * Handle for DRM syncobj that will have its fence replaced with
+	 * the job's completion fence. Ignored if zero.
+	 */
+	__u32 syncobj_out;
+
+	/**
+	 * @syncpt_incr: [in,out]
+	 *
+	 * Information about the syncpoint the job will increment.
+	 */
+	struct drm_tegra_submit_syncpt syncpt;
+};
+
+struct drm_tegra_syncpoint_allocate {
+	/**
+	 * @id: [out]
+	 *
+	 * ID of allocated syncpoint.
+	 */
+	__u32 id;
+	__u32 padding;
+};
+
+struct drm_tegra_syncpoint_free {
+	/**
+	 * @id: [in]
+	 *
+	 * ID of syncpoint to free.
+	 */
+	__u32 id;
+	__u32 padding;
+};
+
+struct drm_tegra_syncpoint_wait {
+	/**
+	 * @timeout: [in]
+	 *
+	 * Absolute timestamp at which the wait will time out.
+	 */
+	__s64 timeout_ns;
+
+	/**
+	 * @id: [in]
+	 *
+	 * ID of syncpoint to wait on.
+	 */
+	__u32 id;
+
+	/**
+	 * @threshold: [in]
+	 *
+	 * Threshold to wait for.
+	 */
+	__u32 threshold;
+
+	/**
+	 * @value: [out]
+	 *
+	 * Value of the syncpoint upon wait completion.
+	 */
+	__u32 value;
+
+	__u32 padding;
+};
+
+#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open)
+#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close)
+#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map)
+#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap)
+#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit)
+
+#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate)
+#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free)
+#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait)
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/prebuilts/arm/include/xf86drmMode.h b/prebuilts/arm/include/xf86drmMode.h
index 19bf91d..4617d1e 100644
--- a/prebuilts/arm/include/xf86drmMode.h
+++ b/prebuilts/arm/include/xf86drmMode.h
@@ -380,6 +380,19 @@ extern drmModeConnectorPtr drmModeGetConnector(int fd,
 extern drmModeConnectorPtr drmModeGetConnectorCurrent(int fd,
 						      uint32_t connector_id);
 
+/**
+ * Get a bitmask of CRTCs a connector is compatible with.
+ *
+ * The bits reference CRTC indices. If the n-th CRTC is compatible with the
+ * connector, the n-th bit will be set. The indices are taken from the array
+ * returned by drmModeGetResources(). The indices are different from the object
+ * IDs.
+ *
+ * Zero is returned on error.
+ */
+extern uint32_t drmModeConnectorGetPossibleCrtcs(int fd,
+                                                 const drmModeConnector *connector);
+
 /**
  * Attaches the given mode to an connector.
  */
@@ -433,18 +446,18 @@ extern int drmModeObjectSetProperty(int fd, uint32_t object_id,
 typedef struct _drmModeAtomicReq drmModeAtomicReq, *drmModeAtomicReqPtr;
 
 extern drmModeAtomicReqPtr drmModeAtomicAlloc(void);
-extern drmModeAtomicReqPtr drmModeAtomicDuplicate(drmModeAtomicReqPtr req);
+extern drmModeAtomicReqPtr drmModeAtomicDuplicate(const drmModeAtomicReqPtr req);
 extern int drmModeAtomicMerge(drmModeAtomicReqPtr base,
-			      drmModeAtomicReqPtr augment);
+			      const drmModeAtomicReqPtr augment);
 extern void drmModeAtomicFree(drmModeAtomicReqPtr req);
-extern int drmModeAtomicGetCursor(drmModeAtomicReqPtr req);
+extern int drmModeAtomicGetCursor(const drmModeAtomicReqPtr req);
 extern void drmModeAtomicSetCursor(drmModeAtomicReqPtr req, int cursor);
 extern int drmModeAtomicAddProperty(drmModeAtomicReqPtr req,
 				    uint32_t object_id,
 				    uint32_t property_id,
 				    uint64_t value);
 extern int drmModeAtomicCommit(int fd,
-			       drmModeAtomicReqPtr req,
+			       const drmModeAtomicReqPtr req,
 			       uint32_t flags,
 			       void *user_data);
 
@@ -475,6 +488,15 @@ extern drmModeObjectListPtr drmModeGetLease(int fd);
 
 extern int drmModeRevokeLease(int fd, uint32_t lessee_id);
 
+/**
+ * Get a string describing a connector type.
+ *
+ * NULL is returned if the connector type is unsupported. Callers should handle
+ * this gracefully, e.g. by falling back to "Unknown" or printing the raw value.
+ */
+extern const char *
+drmModeGetConnectorTypeName(uint32_t connector_type);
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/prebuilts/arm/lib/libdrm.so.2.4.0 b/prebuilts/arm/lib/libdrm.so.2.4.0
index bbba051..7cbc69e 100755
Binary files a/prebuilts/arm/lib/libdrm.so.2.4.0 and b/prebuilts/arm/lib/libdrm.so.2.4.0 differ
diff --git a/prebuilts/arm/lib/libdrm_amdgpu.so.1.0.0 b/prebuilts/arm/lib/libdrm_amdgpu.so.1.0.0
index 5deed68..c46b331 100755
Binary files a/prebuilts/arm/lib/libdrm_amdgpu.so.1.0.0 and b/prebuilts/arm/lib/libdrm_amdgpu.so.1.0.0 differ
diff --git a/prebuilts/arm/lib/libdrm_nouveau.so.2.0.0 b/prebuilts/arm/lib/libdrm_nouveau.so.2.0.0
index e8928b5..b31dd0f 100755
Binary files a/prebuilts/arm/lib/libdrm_nouveau.so.2.0.0 and b/prebuilts/arm/lib/libdrm_nouveau.so.2.0.0 differ
diff --git a/prebuilts/arm/share/amdgpu.ids b/prebuilts/arm/share/amdgpu.ids
deleted file mode 100644
index 0040a38..0000000
--- a/prebuilts/arm/share/amdgpu.ids
+++ /dev/null
@@ -1,300 +0,0 @@
-# List of AMDGPU IDs
-#
-# Syntax:
-# device_id,	revision_id,	product_name        <-- single tab after comma
-
-1.0.0
-15DD,	C3,	AMD Radeon Vega 3 Graphics
-15DD,	CB,	AMD Radeon Vega 3 Graphics
-15DD,	CE,	AMD Radeon Vega 3 Graphics
-15DD,	D8,	AMD Radeon Vega 3 Graphics
-15DD,	CC,	AMD Radeon Vega 6 Graphics
-15DD,	D9,	AMD Radeon Vega 6 Graphics
-15DD,	C2,	AMD Radeon Vega 8 Graphics
-15DD,	C4,	AMD Radeon Vega 8 Graphics
-15DD,	C8,	AMD Radeon Vega 8 Graphics
-15DD,	CA,	AMD Radeon Vega 8 Graphics
-15DD,	D1,	AMD Radeon Vega 8 Graphics
-15DD,	D5,	AMD Radeon Vega 8 Graphics
-15DD,	D7,	AMD Radeon Vega 8 Graphics
-15DD,	C3,	AMD Radeon Vega 10 Graphics
-15DD,	D0,	AMD Radeon Vega 10 Graphics
-15DD,	C1,	AMD Radeon Vega 11 Graphics
-15DD,	C6,	AMD Radeon Vega 11 Graphics
-15DD,	C9,	AMD Radeon Vega 11 Graphics
-15DD,	D3,	AMD Radeon Vega 11 Graphics
-15DD,	D6,	AMD Radeon Vega 11 Graphics
-15DD,	81,	AMD Ryzen Embedded V1807B with Radeon Vega Gfx
-15DD,	82,	AMD Ryzen Embedded V1756B with Radeon Vega Gfx
-15DD,	83,	AMD Ryzen Embedded V1605B with Radeon Vega Gfx
-15DD,	85,	AMD Ryzen Embedded V1202B with Radeon Vega Gfx
-15D8,	93,	AMD Radeon Vega 1 Graphics
-15D8,	C4,	AMD Radeon Vega 3 Graphics
-15D8,	C5,	AMD Radeon Vega 3 Graphics
-15D8,	CC,	AMD Radeon Vega 3 Graphics
-15D8,	CE,	AMD Radeon Vega 3 Graphics
-15D8,	CF,	AMD Radeon Vega 3 Graphics
-15D8,	D4,	AMD Radeon Vega 3 Graphics
-15D8,	DC,	AMD Radeon Vega 3 Graphics
-15D8,	DD,	AMD Radeon Vega 3 Graphics
-15D8,	DE,	AMD Radeon Vega 3 Graphics
-15D8,	DF,	AMD Radeon Vega 3 Graphics
-15D8,	E3,	AMD Radeon Vega 3 Graphics
-15D8,	E4,	AMD Radeon Vega 3 Graphics
-15D8,	A3,	AMD Radeon Vega 6 Graphics
-15D8,	B3,	AMD Radeon Vega 6 Graphics
-15D8,	C3,	AMD Radeon Vega 6 Graphics
-15D8,	D3,	AMD Radeon Vega 6 Graphics
-15D8,	A2,	AMD Radeon Vega 8 Graphics
-15D8,	B2,	AMD Radeon Vega 8 Graphics
-15D8,	C2,	AMD Radeon Vega 8 Graphics
-15D8,	C9,	AMD Radeon Vega 8 Graphics
-15D8,	CB,	AMD Radeon Vega 8 Graphics
-15D8,	D2,	AMD Radeon Vega 8 Graphics
-15D8,	D9,	AMD Radeon Vega 8 Graphics
-15D8,	DB,	AMD Radeon Vega 8 Graphics
-15D8,	A1,	AMD Radeon Vega 10 Graphics
-15D8,	B1,	AMD Radeon Vega 10 Graphics
-15D8,	C1,	AMD Radeon Vega 10 Graphics
-15D8,	D1,	AMD Radeon Vega 10 Graphics
-15D8,	C8,	AMD Radeon Vega 11 Graphics
-15D8,	CA,	AMD Radeon Vega 11 Graphics
-15D8,	D8,	AMD Radeon Vega 11 Graphics
-15D8,	DA,	AMD Radeon Vega 11 Graphics
-15D8,	91,	AMD Ryzen Embedded R1606G with Radeon Vega Gfx
-15D8,	92,	AMD Ryzen Embedded R1505G with Radeon Vega Gfx
-15D8,	CF,	AMD Ryzen Embedded R1305G with Radeon Vega Gfx
-15D8,	E4,	AMD Ryzen Embedded R1102G with Radeon Vega Gfx
-163F,	AE,	AMD Custom GPU 0405
-6600,	0,	AMD Radeon HD 8600 / 8700M
-6600,	81,	AMD Radeon R7 M370
-6601,	0,	AMD Radeon HD 8500M / 8700M
-6604,	0,	AMD Radeon R7 M265 Series
-6604,	81,	AMD Radeon R7 M350
-6605,	0,	AMD Radeon R7 M260 Series
-6605,	81,	AMD Radeon R7 M340
-6606,	0,	AMD Radeon HD 8790M
-6607,	0,	AMD Radeon HD 8530M
-6608,	0,	AMD FirePro W2100
-6610,	0,	AMD Radeon HD 8600 Series
-6610,	81,	AMD Radeon R7 350
-6610,	83,	AMD Radeon R5 340
-6611,	0,	AMD Radeon HD 8500 Series
-6613,	0,	AMD Radeon HD 8500 series
-6617,	C7,	AMD Radeon R7 240 Series
-6640,	0,	AMD Radeon HD 8950
-6640,	80,	AMD Radeon R9 M380
-6646,	0,	AMD Radeon R9 M280X
-6646,	80,	AMD Radeon R9 M470X
-6647,	0,	AMD Radeon R9 M270X
-6647,	80,	AMD Radeon R9 M380
-6649,	0,	AMD FirePro W5100
-6658,	0,	AMD Radeon R7 200 Series
-665C,	0,	AMD Radeon HD 7700 Series
-665D,	0,	AMD Radeon R7 200 Series
-665F,	81,	AMD Radeon R7 300 Series
-6660,	0,	AMD Radeon HD 8600M Series
-6660,	81,	AMD Radeon R5 M335
-6660,	83,	AMD Radeon R5 M330
-6663,	0,	AMD Radeon HD 8500M Series
-6663,	83,	AMD Radeon R5 M320
-6664,	0,	AMD Radeon R5 M200 Series
-6665,	0,	AMD Radeon R5 M200 Series
-6665,	83,	AMD Radeon R5 M320
-6667,	0,	AMD Radeon R5 M200 Series
-666F,	0,	AMD Radeon HD 8500M
-66A1,	06,	AMD Radeon Pro VII
-66AF,	C1,	AMD Radeon VII
-6780,	0,	ATI FirePro V (FireGL V) Graphics Adapter
-678A,	0,	ATI FirePro V (FireGL V) Graphics Adapter
-6798,	0,	AMD Radeon HD 7900 Series
-679A,	0,	AMD Radeon HD 7900 Series
-679B,	0,	AMD Radeon HD 7900 Series
-679E,	0,	AMD Radeon HD 7800 Series
-67A0,	0,	AMD Radeon FirePro W9100
-67A1,	0,	AMD Radeon FirePro W8100
-67B0,	0,	AMD Radeon R9 200 Series
-67B0,	80,	AMD Radeon R9 390 Series
-67B1,	0,	AMD Radeon R9 200 Series
-67B1,	80,	AMD Radeon R9 390 Series
-67B9,	0,	AMD Radeon R9 200 Series
-67DF,	C1,	AMD Radeon RX 580 Series
-67DF,	C2,	AMD Radeon RX 570 Series
-67DF,	C3,	AMD Radeon RX 580 Series
-67DF,	C4,	AMD Radeon RX 480 Graphics
-67DF,	C5,	AMD Radeon RX 470 Graphics
-67DF,	C6,	AMD Radeon RX 570 Series
-67DF,	C7,	AMD Radeon RX 480 Graphics
-67DF,	CF,	AMD Radeon RX 470 Graphics
-67DF,	D7,	AMD Radeon RX 470 Graphics
-67DF,	E0,	AMD Radeon RX 470 Series
-67DF,	E1,	AMD Radeon RX 590 Series
-67DF,	E3,	AMD Radeon RX Series
-67DF,	E7,	AMD Radeon RX 580 Series
-67DF,	EF,	AMD Radeon RX 570 Series
-67DF,	F7,	AMD Radeon RX P30PH
-67C2,	01,	AMD Radeon Pro V7350x2
-67C2,	02,	AMD Radeon Pro V7300X
-67C4,	00,	AMD Radeon Pro WX 7100 Graphics
-67C4,	80,	AMD Radeon E9560 / E9565 Graphics
-67C7,	00,	AMD Radeon Pro WX 5100 Graphics
-67C7,	80,	AMD Radeon E9390 Graphics
-67C0,	00,	AMD Radeon Pro WX 7100 Graphics
-67D0,	01,	AMD Radeon Pro V7350x2
-67D0,	02,	AMD Radeon Pro V7300X
-67E0,	00,	AMD Radeon Pro WX Series
-67E3,	00,	AMD Radeon Pro WX 4100
-67E8,	00,	AMD Radeon Pro WX Series
-67E8,	01,	AMD Radeon Pro WX Series
-67E8,	80,	AMD Radeon E9260 Graphics
-67EB,	00,	AMD Radeon Pro V5300X
-67EF,	C0,	AMD Radeon RX Graphics
-67EF,	C1,	AMD Radeon RX 460 Graphics
-67EF,	C3,	AMD Radeon RX Series
-67EF,	C5,	AMD Radeon RX 460 Graphics
-67EF,	C7,	AMD Radeon RX Graphics
-67EF,	CF,	AMD Radeon RX 460 Graphics
-67EF,	E2,	AMD Radeon RX 560X
-67EF,	E0,	AMD Radeon RX 560 Series
-67EF,	E1,	AMD Radeon RX Series
-67EF,	E3,	AMD Radeon RX Series
-67EF,	E5,	AMD Radeon RX 560 Series
-67EF,	EF,	AMD Radeon RX Graphics
-67EF,	FF,	AMD Radeon RX 460 Graphics
-67FF,	C0,	AMD Radeon RX Graphics
-67FF,	C1,	AMD Radeon RX Graphics
-67FF,	CF,	AMD Radeon RX 560 Series
-67FF,	EF,	AMD Radeon RX 560 Series
-67FF,	FF,	AMD Radeon RX 550 Series
-6800,	0,	AMD Radeon HD 7970M
-6801,	0,	AMD Radeon HD 8970M
-6808,	0,	ATI FirePro V(FireGL V) Graphics Adapter
-6809,	0,	ATI FirePro V(FireGL V) Graphics Adapter
-6810,	0,	AMD Radeon HD 8800 Series
-6810,	81,	AMD Radeon R7 370 Series
-6811,	0,	AMD Radeon HD 8800 Series
-6811,	81,	AMD Radeon R7 300 Series
-6818,	0,	AMD Radeon HD 7800 Series
-6819,	0,	AMD Radeon HD 7800 Series
-6820,	0,	AMD Radeon HD 8800M Series
-6820,	81,	AMD Radeon R9 M375
-6820,	83,	AMD Radeon R9 M375X
-6821,	0,	AMD Radeon HD 8800M Series
-6821,	87,	AMD Radeon R7 M380
-6821,	83,	AMD Radeon R9 M370X
-6822,	0,	AMD Radeon E8860
-6823,	0,	AMD Radeon HD 8800M Series
-6825,	0,	AMD Radeon HD 7800M Series
-6827,	0,	AMD Radeon HD 7800M Series
-6828,	0,	ATI FirePro V(FireGL V) Graphics Adapter
-682B,	0,	AMD Radeon HD 8800M Series
-682B,	87,	AMD Radeon R9 M360
-682C,	0,	AMD FirePro W4100
-682D,	0,	AMD Radeon HD 7700M Series
-682F,	0,	AMD Radeon HD 7700M Series
-6835,	0,	AMD Radeon R7 Series / HD 9000 Series
-6837,	0,	AMD Radeon HD 7700 Series
-683D,	0,	AMD Radeon HD 7700 Series
-683F,	0,	AMD Radeon HD 7700 Series
-6860,	00,	AMD Radeon Instinct MI25
-6860,	01,	AMD Radeon Instinct MI25
-6860,	02,	AMD Radeon Instinct MI25
-6860,	03,	AMD Radeon Pro V340
-6860,	04,	AMD Radeon Instinct MI25x2
-6860,	07,	AMD Radeon Pro V320
-6861,	00,	AMD Radeon Pro WX 9100
-6862,	00,	AMD Radeon Pro SSG
-6863,	00,	AMD Radeon Vega Frontier Edition
-6864,	03,	AMD Radeon Pro V340
-6864,	04,	AMD Radeon Instinct MI25x2
-6868,	00,	AMD Radeon Pro WX 8200
-686C,	00,	AMD Radeon Instinct MI25 MxGPU
-686C,	01,	AMD Radeon Instinct MI25 MxGPU
-686C,	02,	AMD Radeon Instinct MI25 MxGPU
-686C,	03,	AMD Radeon Pro V340 MxGPU
-686C,	04,	AMD Radeon Instinct MI25x2 MxGPU
-686C,	05,	AMD Radeon Pro V340L MxGPU
-686C,	06,	AMD Radeon Instinct MI25 MxGPU
-687F,	C0,	AMD Radeon RX Vega
-687F,	C1,	AMD Radeon RX Vega
-687F,	C3,	AMD Radeon RX Vega
-6900,	0,	AMD Radeon R7 M260
-6900,	81,	AMD Radeon R7 M360
-6900,	83,	AMD Radeon R7 M340
-6901,	0,	AMD Radeon R5 M255
-6907,	0,	AMD Radeon R5 M255
-6907,	87,	AMD Radeon R5 M315
-6920,	0,	AMD Radeon R9 M395X
-6920,	1,	AMD Radeon R9 M390X
-6921,	0,	AMD Radeon R9 M295X
-6929,	0,	AMD FirePro S7150
-692B,	0,	AMD FirePro W7100
-6938,	0,	AMD Radeon R9 200 Series
-6938,	F0,	AMD Radeon R9 200 Series
-6938,	F1,	AMD Radeon R9 380 Series
-6939,	F0,	AMD Radeon R9 200 Series
-6939,	0,	AMD Radeon R9 200 Series
-6939,	F1,	AMD Radeon R9 380 Series
-6980,	00,	AMD Radeon Pro WX 3100
-6981,	00,	AMD Radeon Pro WX 3200 Series
-6981,	01,	AMD Radeon Pro WX 3200 Series
-6981,	10,	AMD Radeon Pro WX 3200 Series
-6985,	00,	AMD Radeon Pro WX 3100
-6987,	80,	AMD Embedded Radeon E9171
-6987,	C0,	AMD Radeon 550X Series
-6987,	C1,	AMD Radeon RX 640
-6987,	C3,	AMD Radeon 540X Series
-6995,	00,	AMD Radeon Pro WX 2100
-6997,	00,	AMD Radeon Pro WX 2100
-699F,	81,	AMD Embedded Radeon E9170 Series
-699F,	C0,	AMD Radeon 500 Series
-699F,	C1,	AMD Radeon 540 Series
-699F,	C3,	AMD Radeon 500 Series
-699F,	C7,	AMD Radeon RX 550 / 550 Series
-7300,	C1,	AMD FirePro S9300 x2
-7300,	C8,	AMD Radeon R9 Fury Series
-7300,	C9,	AMD Radeon Pro Duo
-7300,	CB,	AMD Radeon R9 Fury Series
-7300,	CA,	AMD Radeon R9 Fury Series
-7312,	00,	AMD Radeon Pro W5700
-731E,	C6,	AMD Radeon RX 5700XTB
-731E,	C7,	AMD Radeon RX 5700B
-731F,	C0,	AMD Radeon RX 5700 XT 50th Anniversary
-731F,	C1,	AMD Radeon RX 5700 XT
-731F,	C2,	AMD Radeon RX 5600M
-731F,	C3,	AMD Radeon RX 5700M
-731F,	C4,	AMD Radeon RX 5700
-731F,	C5,	AMD Radeon RX 5700 XT
-731F,	CA,	AMD Radeon RX 5600 XT
-731F,	CB,	AMD Radeon RX 5600 OEM
-7340,	C1,	AMD Radeon RX 5500M
-7340,	C5,	AMD Radeon RX 5500 XT
-7340,	C7,	AMD Radeon RX 5500
-7340,	C9,	AMD Radeon RX 5500XTB
-7340,	CF,	AMD Radeon RX 5300
-7341,	00,	AMD Radeon Pro W5500
-7347,	00,	AMD Radeon Pro W5500M
-73A3,	00,	AMD Radeon Pro W6800
-73AF,	C0,	AMD Radeon RX 6900 XT
-73BF,	C0,	AMD Radeon RX 6900 XT
-73BF,	C1,	AMD Radeon RX 6800 XT
-73BF,	C3,	AMD Radeon RX 6800
-73DF,	C1,	AMD Radeon RX 6700 XT
-73DF,	C3,	AMD Radeon RX 6800M
-73DF,	C5,	AMD Radeon RX 6700 XT
-73DF,	CF,	AMD Radeon RX 6700M
-73E1,	00,	AMD Radeon Pro W6600M
-73E3,	00,	AMD Radeon Pro W6600
-73FF,	C1,	AMD Radeon RX 6600 XT
-73FF,	C3,	AMD Radeon RX 6600M
-9874,	C4,	AMD Radeon R7 Graphics
-9874,	C5,	AMD Radeon R6 Graphics
-9874,	C6,	AMD Radeon R6 Graphics
-9874,	C7,	AMD Radeon R5 Graphics
-9874,	C8,	AMD Radeon R7 Graphics
-9874,	81,	AMD Radeon R6 Graphics
-9874,	87,	AMD Radeon R5 Graphics
-9874,	85,	AMD Radeon R6 Graphics
-9874,	84,	AMD Radeon R7 Graphics
-6FDF,	E7,	AMD Radeon RX 590 GME
-6FDF,	EF,	AMD Radeon RX 580 2048SP
diff --git a/prebuilts/arm/share/libdrm/amdgpu.ids b/prebuilts/arm/share/libdrm/amdgpu.ids
index 0040a38..0d2b884 100644
--- a/prebuilts/arm/share/libdrm/amdgpu.ids
+++ b/prebuilts/arm/share/libdrm/amdgpu.ids
@@ -275,18 +275,35 @@
 7341,	00,	AMD Radeon Pro W5500
 7347,	00,	AMD Radeon Pro W5500M
 73A3,	00,	AMD Radeon Pro W6800
+73A5,	C0,	AMD Radeon RX 6950 XT
 73AF,	C0,	AMD Radeon RX 6900 XT
 73BF,	C0,	AMD Radeon RX 6900 XT
 73BF,	C1,	AMD Radeon RX 6800 XT
 73BF,	C3,	AMD Radeon RX 6800
+73DF,	C0,	AMD Radeon RX 6750 XT
 73DF,	C1,	AMD Radeon RX 6700 XT
 73DF,	C3,	AMD Radeon RX 6800M
 73DF,	C5,	AMD Radeon RX 6700 XT
 73DF,	CF,	AMD Radeon RX 6700M
 73E1,	00,	AMD Radeon Pro W6600M
 73E3,	00,	AMD Radeon Pro W6600
+73EF,	C0,	AMD Radeon RX 6800S
+73EF,	C1,	AMD Radeon RX 6650 XT
+73EF,	C2,	AMD Radeon RX 6700S
+73EF,	C3,	AMD Radeon RX 6650M
+73EF,	C4,	AMD Radeon RX 6650M XT
 73FF,	C1,	AMD Radeon RX 6600 XT
 73FF,	C3,	AMD Radeon RX 6600M
+73FF,	C7,	AMD Radeon RX 6600
+73FF,	CB,	AMD Radeon RX 6600S
+7421,	00,	AMD Radeon Pro W6500M
+7422,	00,	AMD Radeon PRO W6400
+7423,	00,	AMD Radeon Pro W6300M
+7424,	00,	AMD Radeon RX 6300
+743F,	C1,	AMD Radeon RX 6500 XT
+743F,	C3,	AMD Radeon RX 6500
+743F,	C7,	AMD Radeon RX 6400
+743F,	CF,	AMD Radeon RX 6300M
 9874,	C4,	AMD Radeon R7 Graphics
 9874,	C5,	AMD Radeon R6 Graphics
 9874,	C6,	AMD Radeon R6 Graphics
diff --git a/prebuilts/x86/include/libdrm/nouveau/nouveau.h b/prebuilts/x86/include/libdrm/nouveau/nouveau.h
index 335ce77..0c632fe 100644
--- a/prebuilts/x86/include/libdrm/nouveau/nouveau.h
+++ b/prebuilts/x86/include/libdrm/nouveau/nouveau.h
@@ -273,4 +273,8 @@ struct nv04_notify {
 	uint32_t offset;
 	uint32_t length;
 };
+
+bool
+nouveau_check_dead_channel(struct nouveau_drm *, struct nouveau_object *chan);
+
 #endif
diff --git a/prebuilts/x86/include/libdrm/tegra_drm.h b/prebuilts/x86/include/libdrm/tegra_drm.h
index 6c07919..94cfc30 100644
--- a/prebuilts/x86/include/libdrm/tegra_drm.h
+++ b/prebuilts/x86/include/libdrm/tegra_drm.h
@@ -1,27 +1,8 @@
-/*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+/* SPDX-License-Identifier: MIT */
+/* Copyright (c) 2012-2020 NVIDIA Corporation */
 
-#ifndef _TEGRA_DRM_H_
-#define _TEGRA_DRM_H_
+#ifndef _UAPI_TEGRA_DRM_H_
+#define _UAPI_TEGRA_DRM_H_
 
 #include "drm.h"
 
@@ -29,6 +10,8 @@
 extern "C" {
 #endif
 
+/* Tegra DRM legacy UAPI. Only enabled with STAGING */
+
 #define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
 #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
 
@@ -649,8 +632,8 @@ struct drm_tegra_gem_get_flags {
 #define DRM_TEGRA_SYNCPT_READ		0x02
 #define DRM_TEGRA_SYNCPT_INCR		0x03
 #define DRM_TEGRA_SYNCPT_WAIT		0x04
-#define DRM_TEGRA_OPEN_CHANNEL		0x05
-#define DRM_TEGRA_CLOSE_CHANNEL		0x06
+#define DRM_TEGRA_OPEN_CHANNEL	        0x05
+#define DRM_TEGRA_CLOSE_CHANNEL	        0x06
 #define DRM_TEGRA_GET_SYNCPT		0x07
 #define DRM_TEGRA_SUBMIT		0x08
 #define DRM_TEGRA_GET_SYNCPT_BASE	0x09
@@ -674,6 +657,402 @@ struct drm_tegra_gem_get_flags {
 #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
 #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
 
+/* New Tegra DRM UAPI */
+
+/*
+ * Reported by the driver in the `capabilities` field.
+ *
+ * DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent
+ * with regard to the system memory.
+ */
+#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0)
+
+struct drm_tegra_channel_open {
+	/**
+	 * @host1x_class: [in]
+	 *
+	 * Host1x class of the engine that will be programmed using this
+	 * channel.
+	 */
+	__u32 host1x_class;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @context: [out]
+	 *
+	 * Opaque identifier corresponding to the opened channel.
+	 */
+	__u32 context;
+
+	/**
+	 * @version: [out]
+	 *
+	 * Version of the engine hardware. This can be used by userspace
+	 * to determine how the engine needs to be programmed.
+	 */
+	__u32 version;
+
+	/**
+	 * @capabilities: [out]
+	 *
+	 * Flags describing the hardware capabilities.
+	 */
+	__u32 capabilities;
+	__u32 padding;
+};
+
+struct drm_tegra_channel_close {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to close.
+	 */
+	__u32 context;
+	__u32 padding;
+};
+
+/*
+ * Mapping flags that can be used to influence how the mapping is created.
+ *
+ * DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access
+ * DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access
+ */
+#define DRM_TEGRA_CHANNEL_MAP_READ  (1 << 0)
+#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1)
+#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | \
+					  DRM_TEGRA_CHANNEL_MAP_WRITE)
+
+struct drm_tegra_channel_map {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to which make memory available for.
+	 */
+	__u32 context;
+
+	/**
+	 * @handle: [in]
+	 *
+	 * GEM handle of the memory to map.
+	 */
+	__u32 handle;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @mapping: [out]
+	 *
+	 * Identifier corresponding to the mapping, to be used for
+	 * relocations or unmapping later.
+	 */
+	__u32 mapping;
+};
+
+struct drm_tegra_channel_unmap {
+	/**
+	 * @context: [in]
+	 *
+	 * Channel identifier of the channel to unmap memory from.
+	 */
+	__u32 context;
+
+	/**
+	 * @mapping: [in]
+	 *
+	 * Mapping identifier of the memory mapping to unmap.
+	 */
+	__u32 mapping;
+};
+
+/* Submission */
+
+/**
+ * Specify that bit 39 of the patched-in address should be set to switch
+ * swizzling between Tegra and non-Tegra sector layout on systems that store
+ * surfaces in system memory in non-Tegra sector layout.
+ */
+#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0)
+
+struct drm_tegra_submit_buf {
+	/**
+	 * @mapping: [in]
+	 *
+	 * Identifier of the mapping to use in the submission.
+	 */
+	__u32 mapping;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * Information for relocation patching.
+	 */
+	struct {
+		/**
+		 * @target_offset: [in]
+		 *
+		 * Offset from the start of the mapping of the data whose
+		 * address is to be patched into the gather.
+		 */
+		__u64 target_offset;
+
+		/**
+		 * @gather_offset_words: [in]
+		 *
+		 * Offset in words from the start of the gather data to
+		 * where the address should be patched into.
+		 */
+		__u32 gather_offset_words;
+
+		/**
+		 * @shift: [in]
+		 *
+		 * Number of bits the address should be shifted right before
+		 * patching in.
+		 */
+		__u32 shift;
+	} reloc;
+};
+
+/**
+ * Execute `words` words of Host1x opcodes specified in the `gather_data_ptr`
+ * buffer. Each GATHER_UPTR command uses successive words from the buffer.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR		0
+/**
+ * Wait for a syncpoint to reach a value before continuing with further
+ * commands.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT		1
+/**
+ * Wait for a syncpoint to reach a value before continuing with further
+ * commands. The threshold is calculated relative to the start of the job.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE	2
+
+struct drm_tegra_submit_cmd_gather_uptr {
+	__u32 words;
+	__u32 reserved[3];
+};
+
+struct drm_tegra_submit_cmd_wait_syncpt {
+	__u32 id;
+	__u32 value;
+	__u32 reserved[2];
+};
+
+struct drm_tegra_submit_cmd {
+	/**
+	 * @type: [in]
+	 *
+	 * Command type to execute. One of the DRM_TEGRA_SUBMIT_CMD*
+	 * defines.
+	 */
+	__u32 type;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	union {
+		struct drm_tegra_submit_cmd_gather_uptr gather_uptr;
+		struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt;
+		__u32 reserved[4];
+	};
+};
+
+struct drm_tegra_submit_syncpt {
+	/**
+	 * @id: [in]
+	 *
+	 * ID of the syncpoint that the job will increment.
+	 */
+	__u32 id;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @increments: [in]
+	 *
+	 * Number of times the job will increment this syncpoint.
+	 */
+	__u32 increments;
+
+	/**
+	 * @value: [out]
+	 *
+	 * Value the syncpoint will have once the job has completed all
+	 * its specified syncpoint increments.
+	 *
+	 * Note that the kernel may increment the syncpoint before or after
+	 * the job. These increments are not reflected in this field.
+	 *
+	 * If the job hangs or times out, not all of the increments may
+	 * get executed.
+	 */
+	__u32 value;
+};
+
+struct drm_tegra_channel_submit {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to submit this job to.
+	 */
+	__u32 context;
+
+	/**
+	 * @num_bufs: [in]
+	 *
+	 * Number of elements in the `bufs_ptr` array.
+	 */
+	__u32 num_bufs;
+
+	/**
+	 * @num_cmds: [in]
+	 *
+	 * Number of elements in the `cmds_ptr` array.
+	 */
+	__u32 num_cmds;
+
+	/**
+	 * @gather_data_words: [in]
+	 *
+	 * Number of 32-bit words in the `gather_data_ptr` array.
+	 */
+	__u32 gather_data_words;
+
+	/**
+	 * @bufs_ptr: [in]
+	 *
+	 * Pointer to an array of drm_tegra_submit_buf structures.
+	 */
+	__u64 bufs_ptr;
+
+	/**
+	 * @cmds_ptr: [in]
+	 *
+	 * Pointer to an array of drm_tegra_submit_cmd structures.
+	 */
+	__u64 cmds_ptr;
+
+	/**
+	 * @gather_data_ptr: [in]
+	 *
+	 * Pointer to an array of Host1x opcodes to be used by GATHER_UPTR
+	 * commands.
+	 */
+	__u64 gather_data_ptr;
+
+	/**
+	 * @syncobj_in: [in]
+	 *
+	 * Handle for DRM syncobj that will be waited before submission.
+	 * Ignored if zero.
+	 */
+	__u32 syncobj_in;
+
+	/**
+	 * @syncobj_out: [in]
+	 *
+	 * Handle for DRM syncobj that will have its fence replaced with
+	 * the job's completion fence. Ignored if zero.
+	 */
+	__u32 syncobj_out;
+
+	/**
+	 * @syncpt_incr: [in,out]
+	 *
+	 * Information about the syncpoint the job will increment.
+	 */
+	struct drm_tegra_submit_syncpt syncpt;
+};
+
+struct drm_tegra_syncpoint_allocate {
+	/**
+	 * @id: [out]
+	 *
+	 * ID of allocated syncpoint.
+	 */
+	__u32 id;
+	__u32 padding;
+};
+
+struct drm_tegra_syncpoint_free {
+	/**
+	 * @id: [in]
+	 *
+	 * ID of syncpoint to free.
+	 */
+	__u32 id;
+	__u32 padding;
+};
+
+struct drm_tegra_syncpoint_wait {
+	/**
+	 * @timeout: [in]
+	 *
+	 * Absolute timestamp at which the wait will time out.
+	 */
+	__s64 timeout_ns;
+
+	/**
+	 * @id: [in]
+	 *
+	 * ID of syncpoint to wait on.
+	 */
+	__u32 id;
+
+	/**
+	 * @threshold: [in]
+	 *
+	 * Threshold to wait for.
+	 */
+	__u32 threshold;
+
+	/**
+	 * @value: [out]
+	 *
+	 * Value of the syncpoint upon wait completion.
+	 */
+	__u32 value;
+
+	__u32 padding;
+};
+
+#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open)
+#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close)
+#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map)
+#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap)
+#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit)
+
+#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate)
+#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free)
+#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait)
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/prebuilts/x86/include/xf86drmMode.h b/prebuilts/x86/include/xf86drmMode.h
index 19bf91d..4617d1e 100644
--- a/prebuilts/x86/include/xf86drmMode.h
+++ b/prebuilts/x86/include/xf86drmMode.h
@@ -380,6 +380,19 @@ extern drmModeConnectorPtr drmModeGetConnector(int fd,
 extern drmModeConnectorPtr drmModeGetConnectorCurrent(int fd,
 						      uint32_t connector_id);
 
+/**
+ * Get a bitmask of CRTCs a connector is compatible with.
+ *
+ * The bits reference CRTC indices. If the n-th CRTC is compatible with the
+ * connector, the n-th bit will be set. The indices are taken from the array
+ * returned by drmModeGetResources(). The indices are different from the object
+ * IDs.
+ *
+ * Zero is returned on error.
+ */
+extern uint32_t drmModeConnectorGetPossibleCrtcs(int fd,
+                                                 const drmModeConnector *connector);
+
 /**
  * Attaches the given mode to an connector.
  */
@@ -433,18 +446,18 @@ extern int drmModeObjectSetProperty(int fd, uint32_t object_id,
 typedef struct _drmModeAtomicReq drmModeAtomicReq, *drmModeAtomicReqPtr;
 
 extern drmModeAtomicReqPtr drmModeAtomicAlloc(void);
-extern drmModeAtomicReqPtr drmModeAtomicDuplicate(drmModeAtomicReqPtr req);
+extern drmModeAtomicReqPtr drmModeAtomicDuplicate(const drmModeAtomicReqPtr req);
 extern int drmModeAtomicMerge(drmModeAtomicReqPtr base,
-			      drmModeAtomicReqPtr augment);
+			      const drmModeAtomicReqPtr augment);
 extern void drmModeAtomicFree(drmModeAtomicReqPtr req);
-extern int drmModeAtomicGetCursor(drmModeAtomicReqPtr req);
+extern int drmModeAtomicGetCursor(const drmModeAtomicReqPtr req);
 extern void drmModeAtomicSetCursor(drmModeAtomicReqPtr req, int cursor);
 extern int drmModeAtomicAddProperty(drmModeAtomicReqPtr req,
 				    uint32_t object_id,
 				    uint32_t property_id,
 				    uint64_t value);
 extern int drmModeAtomicCommit(int fd,
-			       drmModeAtomicReqPtr req,
+			       const drmModeAtomicReqPtr req,
 			       uint32_t flags,
 			       void *user_data);
 
@@ -475,6 +488,15 @@ extern drmModeObjectListPtr drmModeGetLease(int fd);
 
 extern int drmModeRevokeLease(int fd, uint32_t lessee_id);
 
+/**
+ * Get a string describing a connector type.
+ *
+ * NULL is returned if the connector type is unsupported. Callers should handle
+ * this gracefully, e.g. by falling back to "Unknown" or printing the raw value.
+ */
+extern const char *
+drmModeGetConnectorTypeName(uint32_t connector_type);
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/prebuilts/x86/lib/libdrm.so.2.4.0 b/prebuilts/x86/lib/libdrm.so.2.4.0
index 778bd7c..42ae78a 100755
Binary files a/prebuilts/x86/lib/libdrm.so.2.4.0 and b/prebuilts/x86/lib/libdrm.so.2.4.0 differ
diff --git a/prebuilts/x86/lib/libdrm_amdgpu.so.1.0.0 b/prebuilts/x86/lib/libdrm_amdgpu.so.1.0.0
index 682b318..59c64b3 100755
Binary files a/prebuilts/x86/lib/libdrm_amdgpu.so.1.0.0 and b/prebuilts/x86/lib/libdrm_amdgpu.so.1.0.0 differ
diff --git a/prebuilts/x86/lib/libdrm_intel.so.1.0.0 b/prebuilts/x86/lib/libdrm_intel.so.1.0.0
index 1b59d3f..47faa4b 100755
Binary files a/prebuilts/x86/lib/libdrm_intel.so.1.0.0 and b/prebuilts/x86/lib/libdrm_intel.so.1.0.0 differ
diff --git a/prebuilts/x86/lib/libdrm_nouveau.so.2.0.0 b/prebuilts/x86/lib/libdrm_nouveau.so.2.0.0
index 5fb91cf..8401454 100755
Binary files a/prebuilts/x86/lib/libdrm_nouveau.so.2.0.0 and b/prebuilts/x86/lib/libdrm_nouveau.so.2.0.0 differ
diff --git a/prebuilts/x86/share/amdgpu.ids b/prebuilts/x86/share/amdgpu.ids
deleted file mode 100644
index 0040a38..0000000
--- a/prebuilts/x86/share/amdgpu.ids
+++ /dev/null
@@ -1,300 +0,0 @@
-# List of AMDGPU IDs
-#
-# Syntax:
-# device_id,	revision_id,	product_name        <-- single tab after comma
-
-1.0.0
-15DD,	C3,	AMD Radeon Vega 3 Graphics
-15DD,	CB,	AMD Radeon Vega 3 Graphics
-15DD,	CE,	AMD Radeon Vega 3 Graphics
-15DD,	D8,	AMD Radeon Vega 3 Graphics
-15DD,	CC,	AMD Radeon Vega 6 Graphics
-15DD,	D9,	AMD Radeon Vega 6 Graphics
-15DD,	C2,	AMD Radeon Vega 8 Graphics
-15DD,	C4,	AMD Radeon Vega 8 Graphics
-15DD,	C8,	AMD Radeon Vega 8 Graphics
-15DD,	CA,	AMD Radeon Vega 8 Graphics
-15DD,	D1,	AMD Radeon Vega 8 Graphics
-15DD,	D5,	AMD Radeon Vega 8 Graphics
-15DD,	D7,	AMD Radeon Vega 8 Graphics
-15DD,	C3,	AMD Radeon Vega 10 Graphics
-15DD,	D0,	AMD Radeon Vega 10 Graphics
-15DD,	C1,	AMD Radeon Vega 11 Graphics
-15DD,	C6,	AMD Radeon Vega 11 Graphics
-15DD,	C9,	AMD Radeon Vega 11 Graphics
-15DD,	D3,	AMD Radeon Vega 11 Graphics
-15DD,	D6,	AMD Radeon Vega 11 Graphics
-15DD,	81,	AMD Ryzen Embedded V1807B with Radeon Vega Gfx
-15DD,	82,	AMD Ryzen Embedded V1756B with Radeon Vega Gfx
-15DD,	83,	AMD Ryzen Embedded V1605B with Radeon Vega Gfx
-15DD,	85,	AMD Ryzen Embedded V1202B with Radeon Vega Gfx
-15D8,	93,	AMD Radeon Vega 1 Graphics
-15D8,	C4,	AMD Radeon Vega 3 Graphics
-15D8,	C5,	AMD Radeon Vega 3 Graphics
-15D8,	CC,	AMD Radeon Vega 3 Graphics
-15D8,	CE,	AMD Radeon Vega 3 Graphics
-15D8,	CF,	AMD Radeon Vega 3 Graphics
-15D8,	D4,	AMD Radeon Vega 3 Graphics
-15D8,	DC,	AMD Radeon Vega 3 Graphics
-15D8,	DD,	AMD Radeon Vega 3 Graphics
-15D8,	DE,	AMD Radeon Vega 3 Graphics
-15D8,	DF,	AMD Radeon Vega 3 Graphics
-15D8,	E3,	AMD Radeon Vega 3 Graphics
-15D8,	E4,	AMD Radeon Vega 3 Graphics
-15D8,	A3,	AMD Radeon Vega 6 Graphics
-15D8,	B3,	AMD Radeon Vega 6 Graphics
-15D8,	C3,	AMD Radeon Vega 6 Graphics
-15D8,	D3,	AMD Radeon Vega 6 Graphics
-15D8,	A2,	AMD Radeon Vega 8 Graphics
-15D8,	B2,	AMD Radeon Vega 8 Graphics
-15D8,	C2,	AMD Radeon Vega 8 Graphics
-15D8,	C9,	AMD Radeon Vega 8 Graphics
-15D8,	CB,	AMD Radeon Vega 8 Graphics
-15D8,	D2,	AMD Radeon Vega 8 Graphics
-15D8,	D9,	AMD Radeon Vega 8 Graphics
-15D8,	DB,	AMD Radeon Vega 8 Graphics
-15D8,	A1,	AMD Radeon Vega 10 Graphics
-15D8,	B1,	AMD Radeon Vega 10 Graphics
-15D8,	C1,	AMD Radeon Vega 10 Graphics
-15D8,	D1,	AMD Radeon Vega 10 Graphics
-15D8,	C8,	AMD Radeon Vega 11 Graphics
-15D8,	CA,	AMD Radeon Vega 11 Graphics
-15D8,	D8,	AMD Radeon Vega 11 Graphics
-15D8,	DA,	AMD Radeon Vega 11 Graphics
-15D8,	91,	AMD Ryzen Embedded R1606G with Radeon Vega Gfx
-15D8,	92,	AMD Ryzen Embedded R1505G with Radeon Vega Gfx
-15D8,	CF,	AMD Ryzen Embedded R1305G with Radeon Vega Gfx
-15D8,	E4,	AMD Ryzen Embedded R1102G with Radeon Vega Gfx
-163F,	AE,	AMD Custom GPU 0405
-6600,	0,	AMD Radeon HD 8600 / 8700M
-6600,	81,	AMD Radeon R7 M370
-6601,	0,	AMD Radeon HD 8500M / 8700M
-6604,	0,	AMD Radeon R7 M265 Series
-6604,	81,	AMD Radeon R7 M350
-6605,	0,	AMD Radeon R7 M260 Series
-6605,	81,	AMD Radeon R7 M340
-6606,	0,	AMD Radeon HD 8790M
-6607,	0,	AMD Radeon HD 8530M
-6608,	0,	AMD FirePro W2100
-6610,	0,	AMD Radeon HD 8600 Series
-6610,	81,	AMD Radeon R7 350
-6610,	83,	AMD Radeon R5 340
-6611,	0,	AMD Radeon HD 8500 Series
-6613,	0,	AMD Radeon HD 8500 series
-6617,	C7,	AMD Radeon R7 240 Series
-6640,	0,	AMD Radeon HD 8950
-6640,	80,	AMD Radeon R9 M380
-6646,	0,	AMD Radeon R9 M280X
-6646,	80,	AMD Radeon R9 M470X
-6647,	0,	AMD Radeon R9 M270X
-6647,	80,	AMD Radeon R9 M380
-6649,	0,	AMD FirePro W5100
-6658,	0,	AMD Radeon R7 200 Series
-665C,	0,	AMD Radeon HD 7700 Series
-665D,	0,	AMD Radeon R7 200 Series
-665F,	81,	AMD Radeon R7 300 Series
-6660,	0,	AMD Radeon HD 8600M Series
-6660,	81,	AMD Radeon R5 M335
-6660,	83,	AMD Radeon R5 M330
-6663,	0,	AMD Radeon HD 8500M Series
-6663,	83,	AMD Radeon R5 M320
-6664,	0,	AMD Radeon R5 M200 Series
-6665,	0,	AMD Radeon R5 M200 Series
-6665,	83,	AMD Radeon R5 M320
-6667,	0,	AMD Radeon R5 M200 Series
-666F,	0,	AMD Radeon HD 8500M
-66A1,	06,	AMD Radeon Pro VII
-66AF,	C1,	AMD Radeon VII
-6780,	0,	ATI FirePro V (FireGL V) Graphics Adapter
-678A,	0,	ATI FirePro V (FireGL V) Graphics Adapter
-6798,	0,	AMD Radeon HD 7900 Series
-679A,	0,	AMD Radeon HD 7900 Series
-679B,	0,	AMD Radeon HD 7900 Series
-679E,	0,	AMD Radeon HD 7800 Series
-67A0,	0,	AMD Radeon FirePro W9100
-67A1,	0,	AMD Radeon FirePro W8100
-67B0,	0,	AMD Radeon R9 200 Series
-67B0,	80,	AMD Radeon R9 390 Series
-67B1,	0,	AMD Radeon R9 200 Series
-67B1,	80,	AMD Radeon R9 390 Series
-67B9,	0,	AMD Radeon R9 200 Series
-67DF,	C1,	AMD Radeon RX 580 Series
-67DF,	C2,	AMD Radeon RX 570 Series
-67DF,	C3,	AMD Radeon RX 580 Series
-67DF,	C4,	AMD Radeon RX 480 Graphics
-67DF,	C5,	AMD Radeon RX 470 Graphics
-67DF,	C6,	AMD Radeon RX 570 Series
-67DF,	C7,	AMD Radeon RX 480 Graphics
-67DF,	CF,	AMD Radeon RX 470 Graphics
-67DF,	D7,	AMD Radeon RX 470 Graphics
-67DF,	E0,	AMD Radeon RX 470 Series
-67DF,	E1,	AMD Radeon RX 590 Series
-67DF,	E3,	AMD Radeon RX Series
-67DF,	E7,	AMD Radeon RX 580 Series
-67DF,	EF,	AMD Radeon RX 570 Series
-67DF,	F7,	AMD Radeon RX P30PH
-67C2,	01,	AMD Radeon Pro V7350x2
-67C2,	02,	AMD Radeon Pro V7300X
-67C4,	00,	AMD Radeon Pro WX 7100 Graphics
-67C4,	80,	AMD Radeon E9560 / E9565 Graphics
-67C7,	00,	AMD Radeon Pro WX 5100 Graphics
-67C7,	80,	AMD Radeon E9390 Graphics
-67C0,	00,	AMD Radeon Pro WX 7100 Graphics
-67D0,	01,	AMD Radeon Pro V7350x2
-67D0,	02,	AMD Radeon Pro V7300X
-67E0,	00,	AMD Radeon Pro WX Series
-67E3,	00,	AMD Radeon Pro WX 4100
-67E8,	00,	AMD Radeon Pro WX Series
-67E8,	01,	AMD Radeon Pro WX Series
-67E8,	80,	AMD Radeon E9260 Graphics
-67EB,	00,	AMD Radeon Pro V5300X
-67EF,	C0,	AMD Radeon RX Graphics
-67EF,	C1,	AMD Radeon RX 460 Graphics
-67EF,	C3,	AMD Radeon RX Series
-67EF,	C5,	AMD Radeon RX 460 Graphics
-67EF,	C7,	AMD Radeon RX Graphics
-67EF,	CF,	AMD Radeon RX 460 Graphics
-67EF,	E2,	AMD Radeon RX 560X
-67EF,	E0,	AMD Radeon RX 560 Series
-67EF,	E1,	AMD Radeon RX Series
-67EF,	E3,	AMD Radeon RX Series
-67EF,	E5,	AMD Radeon RX 560 Series
-67EF,	EF,	AMD Radeon RX Graphics
-67EF,	FF,	AMD Radeon RX 460 Graphics
-67FF,	C0,	AMD Radeon RX Graphics
-67FF,	C1,	AMD Radeon RX Graphics
-67FF,	CF,	AMD Radeon RX 560 Series
-67FF,	EF,	AMD Radeon RX 560 Series
-67FF,	FF,	AMD Radeon RX 550 Series
-6800,	0,	AMD Radeon HD 7970M
-6801,	0,	AMD Radeon HD 8970M
-6808,	0,	ATI FirePro V(FireGL V) Graphics Adapter
-6809,	0,	ATI FirePro V(FireGL V) Graphics Adapter
-6810,	0,	AMD Radeon HD 8800 Series
-6810,	81,	AMD Radeon R7 370 Series
-6811,	0,	AMD Radeon HD 8800 Series
-6811,	81,	AMD Radeon R7 300 Series
-6818,	0,	AMD Radeon HD 7800 Series
-6819,	0,	AMD Radeon HD 7800 Series
-6820,	0,	AMD Radeon HD 8800M Series
-6820,	81,	AMD Radeon R9 M375
-6820,	83,	AMD Radeon R9 M375X
-6821,	0,	AMD Radeon HD 8800M Series
-6821,	87,	AMD Radeon R7 M380
-6821,	83,	AMD Radeon R9 M370X
-6822,	0,	AMD Radeon E8860
-6823,	0,	AMD Radeon HD 8800M Series
-6825,	0,	AMD Radeon HD 7800M Series
-6827,	0,	AMD Radeon HD 7800M Series
-6828,	0,	ATI FirePro V(FireGL V) Graphics Adapter
-682B,	0,	AMD Radeon HD 8800M Series
-682B,	87,	AMD Radeon R9 M360
-682C,	0,	AMD FirePro W4100
-682D,	0,	AMD Radeon HD 7700M Series
-682F,	0,	AMD Radeon HD 7700M Series
-6835,	0,	AMD Radeon R7 Series / HD 9000 Series
-6837,	0,	AMD Radeon HD 7700 Series
-683D,	0,	AMD Radeon HD 7700 Series
-683F,	0,	AMD Radeon HD 7700 Series
-6860,	00,	AMD Radeon Instinct MI25
-6860,	01,	AMD Radeon Instinct MI25
-6860,	02,	AMD Radeon Instinct MI25
-6860,	03,	AMD Radeon Pro V340
-6860,	04,	AMD Radeon Instinct MI25x2
-6860,	07,	AMD Radeon Pro V320
-6861,	00,	AMD Radeon Pro WX 9100
-6862,	00,	AMD Radeon Pro SSG
-6863,	00,	AMD Radeon Vega Frontier Edition
-6864,	03,	AMD Radeon Pro V340
-6864,	04,	AMD Radeon Instinct MI25x2
-6868,	00,	AMD Radeon Pro WX 8200
-686C,	00,	AMD Radeon Instinct MI25 MxGPU
-686C,	01,	AMD Radeon Instinct MI25 MxGPU
-686C,	02,	AMD Radeon Instinct MI25 MxGPU
-686C,	03,	AMD Radeon Pro V340 MxGPU
-686C,	04,	AMD Radeon Instinct MI25x2 MxGPU
-686C,	05,	AMD Radeon Pro V340L MxGPU
-686C,	06,	AMD Radeon Instinct MI25 MxGPU
-687F,	C0,	AMD Radeon RX Vega
-687F,	C1,	AMD Radeon RX Vega
-687F,	C3,	AMD Radeon RX Vega
-6900,	0,	AMD Radeon R7 M260
-6900,	81,	AMD Radeon R7 M360
-6900,	83,	AMD Radeon R7 M340
-6901,	0,	AMD Radeon R5 M255
-6907,	0,	AMD Radeon R5 M255
-6907,	87,	AMD Radeon R5 M315
-6920,	0,	AMD Radeon R9 M395X
-6920,	1,	AMD Radeon R9 M390X
-6921,	0,	AMD Radeon R9 M295X
-6929,	0,	AMD FirePro S7150
-692B,	0,	AMD FirePro W7100
-6938,	0,	AMD Radeon R9 200 Series
-6938,	F0,	AMD Radeon R9 200 Series
-6938,	F1,	AMD Radeon R9 380 Series
-6939,	F0,	AMD Radeon R9 200 Series
-6939,	0,	AMD Radeon R9 200 Series
-6939,	F1,	AMD Radeon R9 380 Series
-6980,	00,	AMD Radeon Pro WX 3100
-6981,	00,	AMD Radeon Pro WX 3200 Series
-6981,	01,	AMD Radeon Pro WX 3200 Series
-6981,	10,	AMD Radeon Pro WX 3200 Series
-6985,	00,	AMD Radeon Pro WX 3100
-6987,	80,	AMD Embedded Radeon E9171
-6987,	C0,	AMD Radeon 550X Series
-6987,	C1,	AMD Radeon RX 640
-6987,	C3,	AMD Radeon 540X Series
-6995,	00,	AMD Radeon Pro WX 2100
-6997,	00,	AMD Radeon Pro WX 2100
-699F,	81,	AMD Embedded Radeon E9170 Series
-699F,	C0,	AMD Radeon 500 Series
-699F,	C1,	AMD Radeon 540 Series
-699F,	C3,	AMD Radeon 500 Series
-699F,	C7,	AMD Radeon RX 550 / 550 Series
-7300,	C1,	AMD FirePro S9300 x2
-7300,	C8,	AMD Radeon R9 Fury Series
-7300,	C9,	AMD Radeon Pro Duo
-7300,	CB,	AMD Radeon R9 Fury Series
-7300,	CA,	AMD Radeon R9 Fury Series
-7312,	00,	AMD Radeon Pro W5700
-731E,	C6,	AMD Radeon RX 5700XTB
-731E,	C7,	AMD Radeon RX 5700B
-731F,	C0,	AMD Radeon RX 5700 XT 50th Anniversary
-731F,	C1,	AMD Radeon RX 5700 XT
-731F,	C2,	AMD Radeon RX 5600M
-731F,	C3,	AMD Radeon RX 5700M
-731F,	C4,	AMD Radeon RX 5700
-731F,	C5,	AMD Radeon RX 5700 XT
-731F,	CA,	AMD Radeon RX 5600 XT
-731F,	CB,	AMD Radeon RX 5600 OEM
-7340,	C1,	AMD Radeon RX 5500M
-7340,	C5,	AMD Radeon RX 5500 XT
-7340,	C7,	AMD Radeon RX 5500
-7340,	C9,	AMD Radeon RX 5500XTB
-7340,	CF,	AMD Radeon RX 5300
-7341,	00,	AMD Radeon Pro W5500
-7347,	00,	AMD Radeon Pro W5500M
-73A3,	00,	AMD Radeon Pro W6800
-73AF,	C0,	AMD Radeon RX 6900 XT
-73BF,	C0,	AMD Radeon RX 6900 XT
-73BF,	C1,	AMD Radeon RX 6800 XT
-73BF,	C3,	AMD Radeon RX 6800
-73DF,	C1,	AMD Radeon RX 6700 XT
-73DF,	C3,	AMD Radeon RX 6800M
-73DF,	C5,	AMD Radeon RX 6700 XT
-73DF,	CF,	AMD Radeon RX 6700M
-73E1,	00,	AMD Radeon Pro W6600M
-73E3,	00,	AMD Radeon Pro W6600
-73FF,	C1,	AMD Radeon RX 6600 XT
-73FF,	C3,	AMD Radeon RX 6600M
-9874,	C4,	AMD Radeon R7 Graphics
-9874,	C5,	AMD Radeon R6 Graphics
-9874,	C6,	AMD Radeon R6 Graphics
-9874,	C7,	AMD Radeon R5 Graphics
-9874,	C8,	AMD Radeon R7 Graphics
-9874,	81,	AMD Radeon R6 Graphics
-9874,	87,	AMD Radeon R5 Graphics
-9874,	85,	AMD Radeon R6 Graphics
-9874,	84,	AMD Radeon R7 Graphics
-6FDF,	E7,	AMD Radeon RX 590 GME
-6FDF,	EF,	AMD Radeon RX 580 2048SP
diff --git a/prebuilts/x86/share/libdrm/amdgpu.ids b/prebuilts/x86/share/libdrm/amdgpu.ids
index 0040a38..0d2b884 100644
--- a/prebuilts/x86/share/libdrm/amdgpu.ids
+++ b/prebuilts/x86/share/libdrm/amdgpu.ids
@@ -275,18 +275,35 @@
 7341,	00,	AMD Radeon Pro W5500
 7347,	00,	AMD Radeon Pro W5500M
 73A3,	00,	AMD Radeon Pro W6800
+73A5,	C0,	AMD Radeon RX 6950 XT
 73AF,	C0,	AMD Radeon RX 6900 XT
 73BF,	C0,	AMD Radeon RX 6900 XT
 73BF,	C1,	AMD Radeon RX 6800 XT
 73BF,	C3,	AMD Radeon RX 6800
+73DF,	C0,	AMD Radeon RX 6750 XT
 73DF,	C1,	AMD Radeon RX 6700 XT
 73DF,	C3,	AMD Radeon RX 6800M
 73DF,	C5,	AMD Radeon RX 6700 XT
 73DF,	CF,	AMD Radeon RX 6700M
 73E1,	00,	AMD Radeon Pro W6600M
 73E3,	00,	AMD Radeon Pro W6600
+73EF,	C0,	AMD Radeon RX 6800S
+73EF,	C1,	AMD Radeon RX 6650 XT
+73EF,	C2,	AMD Radeon RX 6700S
+73EF,	C3,	AMD Radeon RX 6650M
+73EF,	C4,	AMD Radeon RX 6650M XT
 73FF,	C1,	AMD Radeon RX 6600 XT
 73FF,	C3,	AMD Radeon RX 6600M
+73FF,	C7,	AMD Radeon RX 6600
+73FF,	CB,	AMD Radeon RX 6600S
+7421,	00,	AMD Radeon Pro W6500M
+7422,	00,	AMD Radeon PRO W6400
+7423,	00,	AMD Radeon Pro W6300M
+7424,	00,	AMD Radeon RX 6300
+743F,	C1,	AMD Radeon RX 6500 XT
+743F,	C3,	AMD Radeon RX 6500
+743F,	C7,	AMD Radeon RX 6400
+743F,	CF,	AMD Radeon RX 6300M
 9874,	C4,	AMD Radeon R7 Graphics
 9874,	C5,	AMD Radeon R6 Graphics
 9874,	C6,	AMD Radeon R6 Graphics
diff --git a/prebuilts/x86_64/include/libdrm/nouveau/nouveau.h b/prebuilts/x86_64/include/libdrm/nouveau/nouveau.h
index 335ce77..0c632fe 100644
--- a/prebuilts/x86_64/include/libdrm/nouveau/nouveau.h
+++ b/prebuilts/x86_64/include/libdrm/nouveau/nouveau.h
@@ -273,4 +273,8 @@ struct nv04_notify {
 	uint32_t offset;
 	uint32_t length;
 };
+
+bool
+nouveau_check_dead_channel(struct nouveau_drm *, struct nouveau_object *chan);
+
 #endif
diff --git a/prebuilts/x86_64/include/libdrm/tegra_drm.h b/prebuilts/x86_64/include/libdrm/tegra_drm.h
index 6c07919..94cfc30 100644
--- a/prebuilts/x86_64/include/libdrm/tegra_drm.h
+++ b/prebuilts/x86_64/include/libdrm/tegra_drm.h
@@ -1,27 +1,8 @@
-/*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+/* SPDX-License-Identifier: MIT */
+/* Copyright (c) 2012-2020 NVIDIA Corporation */
 
-#ifndef _TEGRA_DRM_H_
-#define _TEGRA_DRM_H_
+#ifndef _UAPI_TEGRA_DRM_H_
+#define _UAPI_TEGRA_DRM_H_
 
 #include "drm.h"
 
@@ -29,6 +10,8 @@
 extern "C" {
 #endif
 
+/* Tegra DRM legacy UAPI. Only enabled with STAGING */
+
 #define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
 #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
 
@@ -649,8 +632,8 @@ struct drm_tegra_gem_get_flags {
 #define DRM_TEGRA_SYNCPT_READ		0x02
 #define DRM_TEGRA_SYNCPT_INCR		0x03
 #define DRM_TEGRA_SYNCPT_WAIT		0x04
-#define DRM_TEGRA_OPEN_CHANNEL		0x05
-#define DRM_TEGRA_CLOSE_CHANNEL		0x06
+#define DRM_TEGRA_OPEN_CHANNEL	        0x05
+#define DRM_TEGRA_CLOSE_CHANNEL	        0x06
 #define DRM_TEGRA_GET_SYNCPT		0x07
 #define DRM_TEGRA_SUBMIT		0x08
 #define DRM_TEGRA_GET_SYNCPT_BASE	0x09
@@ -674,6 +657,402 @@ struct drm_tegra_gem_get_flags {
 #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
 #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
 
+/* New Tegra DRM UAPI */
+
+/*
+ * Reported by the driver in the `capabilities` field.
+ *
+ * DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent
+ * with regard to the system memory.
+ */
+#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0)
+
+struct drm_tegra_channel_open {
+	/**
+	 * @host1x_class: [in]
+	 *
+	 * Host1x class of the engine that will be programmed using this
+	 * channel.
+	 */
+	__u32 host1x_class;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @context: [out]
+	 *
+	 * Opaque identifier corresponding to the opened channel.
+	 */
+	__u32 context;
+
+	/**
+	 * @version: [out]
+	 *
+	 * Version of the engine hardware. This can be used by userspace
+	 * to determine how the engine needs to be programmed.
+	 */
+	__u32 version;
+
+	/**
+	 * @capabilities: [out]
+	 *
+	 * Flags describing the hardware capabilities.
+	 */
+	__u32 capabilities;
+	__u32 padding;
+};
+
+struct drm_tegra_channel_close {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to close.
+	 */
+	__u32 context;
+	__u32 padding;
+};
+
+/*
+ * Mapping flags that can be used to influence how the mapping is created.
+ *
+ * DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access
+ * DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access
+ */
+#define DRM_TEGRA_CHANNEL_MAP_READ  (1 << 0)
+#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1)
+#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | \
+					  DRM_TEGRA_CHANNEL_MAP_WRITE)
+
+struct drm_tegra_channel_map {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to which make memory available for.
+	 */
+	__u32 context;
+
+	/**
+	 * @handle: [in]
+	 *
+	 * GEM handle of the memory to map.
+	 */
+	__u32 handle;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @mapping: [out]
+	 *
+	 * Identifier corresponding to the mapping, to be used for
+	 * relocations or unmapping later.
+	 */
+	__u32 mapping;
+};
+
+struct drm_tegra_channel_unmap {
+	/**
+	 * @context: [in]
+	 *
+	 * Channel identifier of the channel to unmap memory from.
+	 */
+	__u32 context;
+
+	/**
+	 * @mapping: [in]
+	 *
+	 * Mapping identifier of the memory mapping to unmap.
+	 */
+	__u32 mapping;
+};
+
+/* Submission */
+
+/**
+ * Specify that bit 39 of the patched-in address should be set to switch
+ * swizzling between Tegra and non-Tegra sector layout on systems that store
+ * surfaces in system memory in non-Tegra sector layout.
+ */
+#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0)
+
+struct drm_tegra_submit_buf {
+	/**
+	 * @mapping: [in]
+	 *
+	 * Identifier of the mapping to use in the submission.
+	 */
+	__u32 mapping;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * Information for relocation patching.
+	 */
+	struct {
+		/**
+		 * @target_offset: [in]
+		 *
+		 * Offset from the start of the mapping of the data whose
+		 * address is to be patched into the gather.
+		 */
+		__u64 target_offset;
+
+		/**
+		 * @gather_offset_words: [in]
+		 *
+		 * Offset in words from the start of the gather data to
+		 * where the address should be patched into.
+		 */
+		__u32 gather_offset_words;
+
+		/**
+		 * @shift: [in]
+		 *
+		 * Number of bits the address should be shifted right before
+		 * patching in.
+		 */
+		__u32 shift;
+	} reloc;
+};
+
+/**
+ * Execute `words` words of Host1x opcodes specified in the `gather_data_ptr`
+ * buffer. Each GATHER_UPTR command uses successive words from the buffer.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR		0
+/**
+ * Wait for a syncpoint to reach a value before continuing with further
+ * commands.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT		1
+/**
+ * Wait for a syncpoint to reach a value before continuing with further
+ * commands. The threshold is calculated relative to the start of the job.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE	2
+
+struct drm_tegra_submit_cmd_gather_uptr {
+	__u32 words;
+	__u32 reserved[3];
+};
+
+struct drm_tegra_submit_cmd_wait_syncpt {
+	__u32 id;
+	__u32 value;
+	__u32 reserved[2];
+};
+
+struct drm_tegra_submit_cmd {
+	/**
+	 * @type: [in]
+	 *
+	 * Command type to execute. One of the DRM_TEGRA_SUBMIT_CMD*
+	 * defines.
+	 */
+	__u32 type;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	union {
+		struct drm_tegra_submit_cmd_gather_uptr gather_uptr;
+		struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt;
+		__u32 reserved[4];
+	};
+};
+
+struct drm_tegra_submit_syncpt {
+	/**
+	 * @id: [in]
+	 *
+	 * ID of the syncpoint that the job will increment.
+	 */
+	__u32 id;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @increments: [in]
+	 *
+	 * Number of times the job will increment this syncpoint.
+	 */
+	__u32 increments;
+
+	/**
+	 * @value: [out]
+	 *
+	 * Value the syncpoint will have once the job has completed all
+	 * its specified syncpoint increments.
+	 *
+	 * Note that the kernel may increment the syncpoint before or after
+	 * the job. These increments are not reflected in this field.
+	 *
+	 * If the job hangs or times out, not all of the increments may
+	 * get executed.
+	 */
+	__u32 value;
+};
+
+struct drm_tegra_channel_submit {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to submit this job to.
+	 */
+	__u32 context;
+
+	/**
+	 * @num_bufs: [in]
+	 *
+	 * Number of elements in the `bufs_ptr` array.
+	 */
+	__u32 num_bufs;
+
+	/**
+	 * @num_cmds: [in]
+	 *
+	 * Number of elements in the `cmds_ptr` array.
+	 */
+	__u32 num_cmds;
+
+	/**
+	 * @gather_data_words: [in]
+	 *
+	 * Number of 32-bit words in the `gather_data_ptr` array.
+	 */
+	__u32 gather_data_words;
+
+	/**
+	 * @bufs_ptr: [in]
+	 *
+	 * Pointer to an array of drm_tegra_submit_buf structures.
+	 */
+	__u64 bufs_ptr;
+
+	/**
+	 * @cmds_ptr: [in]
+	 *
+	 * Pointer to an array of drm_tegra_submit_cmd structures.
+	 */
+	__u64 cmds_ptr;
+
+	/**
+	 * @gather_data_ptr: [in]
+	 *
+	 * Pointer to an array of Host1x opcodes to be used by GATHER_UPTR
+	 * commands.
+	 */
+	__u64 gather_data_ptr;
+
+	/**
+	 * @syncobj_in: [in]
+	 *
+	 * Handle for DRM syncobj that will be waited before submission.
+	 * Ignored if zero.
+	 */
+	__u32 syncobj_in;
+
+	/**
+	 * @syncobj_out: [in]
+	 *
+	 * Handle for DRM syncobj that will have its fence replaced with
+	 * the job's completion fence. Ignored if zero.
+	 */
+	__u32 syncobj_out;
+
+	/**
+	 * @syncpt_incr: [in,out]
+	 *
+	 * Information about the syncpoint the job will increment.
+	 */
+	struct drm_tegra_submit_syncpt syncpt;
+};
+
+struct drm_tegra_syncpoint_allocate {
+	/**
+	 * @id: [out]
+	 *
+	 * ID of allocated syncpoint.
+	 */
+	__u32 id;
+	__u32 padding;
+};
+
+struct drm_tegra_syncpoint_free {
+	/**
+	 * @id: [in]
+	 *
+	 * ID of syncpoint to free.
+	 */
+	__u32 id;
+	__u32 padding;
+};
+
+struct drm_tegra_syncpoint_wait {
+	/**
+	 * @timeout: [in]
+	 *
+	 * Absolute timestamp at which the wait will time out.
+	 */
+	__s64 timeout_ns;
+
+	/**
+	 * @id: [in]
+	 *
+	 * ID of syncpoint to wait on.
+	 */
+	__u32 id;
+
+	/**
+	 * @threshold: [in]
+	 *
+	 * Threshold to wait for.
+	 */
+	__u32 threshold;
+
+	/**
+	 * @value: [out]
+	 *
+	 * Value of the syncpoint upon wait completion.
+	 */
+	__u32 value;
+
+	__u32 padding;
+};
+
+#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open)
+#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close)
+#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map)
+#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap)
+#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit)
+
+#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate)
+#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free)
+#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait)
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/prebuilts/x86_64/include/xf86drmMode.h b/prebuilts/x86_64/include/xf86drmMode.h
index 19bf91d..4617d1e 100644
--- a/prebuilts/x86_64/include/xf86drmMode.h
+++ b/prebuilts/x86_64/include/xf86drmMode.h
@@ -380,6 +380,19 @@ extern drmModeConnectorPtr drmModeGetConnector(int fd,
 extern drmModeConnectorPtr drmModeGetConnectorCurrent(int fd,
 						      uint32_t connector_id);
 
+/**
+ * Get a bitmask of CRTCs a connector is compatible with.
+ *
+ * The bits reference CRTC indices. If the n-th CRTC is compatible with the
+ * connector, the n-th bit will be set. The indices are taken from the array
+ * returned by drmModeGetResources(). The indices are different from the object
+ * IDs.
+ *
+ * Zero is returned on error.
+ */
+extern uint32_t drmModeConnectorGetPossibleCrtcs(int fd,
+                                                 const drmModeConnector *connector);
+
 /**
  * Attaches the given mode to an connector.
  */
@@ -433,18 +446,18 @@ extern int drmModeObjectSetProperty(int fd, uint32_t object_id,
 typedef struct _drmModeAtomicReq drmModeAtomicReq, *drmModeAtomicReqPtr;
 
 extern drmModeAtomicReqPtr drmModeAtomicAlloc(void);
-extern drmModeAtomicReqPtr drmModeAtomicDuplicate(drmModeAtomicReqPtr req);
+extern drmModeAtomicReqPtr drmModeAtomicDuplicate(const drmModeAtomicReqPtr req);
 extern int drmModeAtomicMerge(drmModeAtomicReqPtr base,
-			      drmModeAtomicReqPtr augment);
+			      const drmModeAtomicReqPtr augment);
 extern void drmModeAtomicFree(drmModeAtomicReqPtr req);
-extern int drmModeAtomicGetCursor(drmModeAtomicReqPtr req);
+extern int drmModeAtomicGetCursor(const drmModeAtomicReqPtr req);
 extern void drmModeAtomicSetCursor(drmModeAtomicReqPtr req, int cursor);
 extern int drmModeAtomicAddProperty(drmModeAtomicReqPtr req,
 				    uint32_t object_id,
 				    uint32_t property_id,
 				    uint64_t value);
 extern int drmModeAtomicCommit(int fd,
-			       drmModeAtomicReqPtr req,
+			       const drmModeAtomicReqPtr req,
 			       uint32_t flags,
 			       void *user_data);
 
@@ -475,6 +488,15 @@ extern drmModeObjectListPtr drmModeGetLease(int fd);
 
 extern int drmModeRevokeLease(int fd, uint32_t lessee_id);
 
+/**
+ * Get a string describing a connector type.
+ *
+ * NULL is returned if the connector type is unsupported. Callers should handle
+ * this gracefully, e.g. by falling back to "Unknown" or printing the raw value.
+ */
+extern const char *
+drmModeGetConnectorTypeName(uint32_t connector_type);
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/prebuilts/x86_64/lib/libdrm.so.2.4.0 b/prebuilts/x86_64/lib/libdrm.so.2.4.0
index 23bcebc..7d7bcbd 100755
Binary files a/prebuilts/x86_64/lib/libdrm.so.2.4.0 and b/prebuilts/x86_64/lib/libdrm.so.2.4.0 differ
diff --git a/prebuilts/x86_64/lib/libdrm_amdgpu.so.1.0.0 b/prebuilts/x86_64/lib/libdrm_amdgpu.so.1.0.0
index b6e551d..37e86b8 100755
Binary files a/prebuilts/x86_64/lib/libdrm_amdgpu.so.1.0.0 and b/prebuilts/x86_64/lib/libdrm_amdgpu.so.1.0.0 differ
diff --git a/prebuilts/x86_64/lib/libdrm_intel.so.1.0.0 b/prebuilts/x86_64/lib/libdrm_intel.so.1.0.0
index c8bf4db..d900e97 100755
Binary files a/prebuilts/x86_64/lib/libdrm_intel.so.1.0.0 and b/prebuilts/x86_64/lib/libdrm_intel.so.1.0.0 differ
diff --git a/prebuilts/x86_64/lib/libdrm_nouveau.so.2.0.0 b/prebuilts/x86_64/lib/libdrm_nouveau.so.2.0.0
index 4efb825..9c95009 100755
Binary files a/prebuilts/x86_64/lib/libdrm_nouveau.so.2.0.0 and b/prebuilts/x86_64/lib/libdrm_nouveau.so.2.0.0 differ
diff --git a/prebuilts/x86_64/share/amdgpu.ids b/prebuilts/x86_64/share/amdgpu.ids
deleted file mode 100644
index 0040a38..0000000
--- a/prebuilts/x86_64/share/amdgpu.ids
+++ /dev/null
@@ -1,300 +0,0 @@
-# List of AMDGPU IDs
-#
-# Syntax:
-# device_id,	revision_id,	product_name        <-- single tab after comma
-
-1.0.0
-15DD,	C3,	AMD Radeon Vega 3 Graphics
-15DD,	CB,	AMD Radeon Vega 3 Graphics
-15DD,	CE,	AMD Radeon Vega 3 Graphics
-15DD,	D8,	AMD Radeon Vega 3 Graphics
-15DD,	CC,	AMD Radeon Vega 6 Graphics
-15DD,	D9,	AMD Radeon Vega 6 Graphics
-15DD,	C2,	AMD Radeon Vega 8 Graphics
-15DD,	C4,	AMD Radeon Vega 8 Graphics
-15DD,	C8,	AMD Radeon Vega 8 Graphics
-15DD,	CA,	AMD Radeon Vega 8 Graphics
-15DD,	D1,	AMD Radeon Vega 8 Graphics
-15DD,	D5,	AMD Radeon Vega 8 Graphics
-15DD,	D7,	AMD Radeon Vega 8 Graphics
-15DD,	C3,	AMD Radeon Vega 10 Graphics
-15DD,	D0,	AMD Radeon Vega 10 Graphics
-15DD,	C1,	AMD Radeon Vega 11 Graphics
-15DD,	C6,	AMD Radeon Vega 11 Graphics
-15DD,	C9,	AMD Radeon Vega 11 Graphics
-15DD,	D3,	AMD Radeon Vega 11 Graphics
-15DD,	D6,	AMD Radeon Vega 11 Graphics
-15DD,	81,	AMD Ryzen Embedded V1807B with Radeon Vega Gfx
-15DD,	82,	AMD Ryzen Embedded V1756B with Radeon Vega Gfx
-15DD,	83,	AMD Ryzen Embedded V1605B with Radeon Vega Gfx
-15DD,	85,	AMD Ryzen Embedded V1202B with Radeon Vega Gfx
-15D8,	93,	AMD Radeon Vega 1 Graphics
-15D8,	C4,	AMD Radeon Vega 3 Graphics
-15D8,	C5,	AMD Radeon Vega 3 Graphics
-15D8,	CC,	AMD Radeon Vega 3 Graphics
-15D8,	CE,	AMD Radeon Vega 3 Graphics
-15D8,	CF,	AMD Radeon Vega 3 Graphics
-15D8,	D4,	AMD Radeon Vega 3 Graphics
-15D8,	DC,	AMD Radeon Vega 3 Graphics
-15D8,	DD,	AMD Radeon Vega 3 Graphics
-15D8,	DE,	AMD Radeon Vega 3 Graphics
-15D8,	DF,	AMD Radeon Vega 3 Graphics
-15D8,	E3,	AMD Radeon Vega 3 Graphics
-15D8,	E4,	AMD Radeon Vega 3 Graphics
-15D8,	A3,	AMD Radeon Vega 6 Graphics
-15D8,	B3,	AMD Radeon Vega 6 Graphics
-15D8,	C3,	AMD Radeon Vega 6 Graphics
-15D8,	D3,	AMD Radeon Vega 6 Graphics
-15D8,	A2,	AMD Radeon Vega 8 Graphics
-15D8,	B2,	AMD Radeon Vega 8 Graphics
-15D8,	C2,	AMD Radeon Vega 8 Graphics
-15D8,	C9,	AMD Radeon Vega 8 Graphics
-15D8,	CB,	AMD Radeon Vega 8 Graphics
-15D8,	D2,	AMD Radeon Vega 8 Graphics
-15D8,	D9,	AMD Radeon Vega 8 Graphics
-15D8,	DB,	AMD Radeon Vega 8 Graphics
-15D8,	A1,	AMD Radeon Vega 10 Graphics
-15D8,	B1,	AMD Radeon Vega 10 Graphics
-15D8,	C1,	AMD Radeon Vega 10 Graphics
-15D8,	D1,	AMD Radeon Vega 10 Graphics
-15D8,	C8,	AMD Radeon Vega 11 Graphics
-15D8,	CA,	AMD Radeon Vega 11 Graphics
-15D8,	D8,	AMD Radeon Vega 11 Graphics
-15D8,	DA,	AMD Radeon Vega 11 Graphics
-15D8,	91,	AMD Ryzen Embedded R1606G with Radeon Vega Gfx
-15D8,	92,	AMD Ryzen Embedded R1505G with Radeon Vega Gfx
-15D8,	CF,	AMD Ryzen Embedded R1305G with Radeon Vega Gfx
-15D8,	E4,	AMD Ryzen Embedded R1102G with Radeon Vega Gfx
-163F,	AE,	AMD Custom GPU 0405
-6600,	0,	AMD Radeon HD 8600 / 8700M
-6600,	81,	AMD Radeon R7 M370
-6601,	0,	AMD Radeon HD 8500M / 8700M
-6604,	0,	AMD Radeon R7 M265 Series
-6604,	81,	AMD Radeon R7 M350
-6605,	0,	AMD Radeon R7 M260 Series
-6605,	81,	AMD Radeon R7 M340
-6606,	0,	AMD Radeon HD 8790M
-6607,	0,	AMD Radeon HD 8530M
-6608,	0,	AMD FirePro W2100
-6610,	0,	AMD Radeon HD 8600 Series
-6610,	81,	AMD Radeon R7 350
-6610,	83,	AMD Radeon R5 340
-6611,	0,	AMD Radeon HD 8500 Series
-6613,	0,	AMD Radeon HD 8500 series
-6617,	C7,	AMD Radeon R7 240 Series
-6640,	0,	AMD Radeon HD 8950
-6640,	80,	AMD Radeon R9 M380
-6646,	0,	AMD Radeon R9 M280X
-6646,	80,	AMD Radeon R9 M470X
-6647,	0,	AMD Radeon R9 M270X
-6647,	80,	AMD Radeon R9 M380
-6649,	0,	AMD FirePro W5100
-6658,	0,	AMD Radeon R7 200 Series
-665C,	0,	AMD Radeon HD 7700 Series
-665D,	0,	AMD Radeon R7 200 Series
-665F,	81,	AMD Radeon R7 300 Series
-6660,	0,	AMD Radeon HD 8600M Series
-6660,	81,	AMD Radeon R5 M335
-6660,	83,	AMD Radeon R5 M330
-6663,	0,	AMD Radeon HD 8500M Series
-6663,	83,	AMD Radeon R5 M320
-6664,	0,	AMD Radeon R5 M200 Series
-6665,	0,	AMD Radeon R5 M200 Series
-6665,	83,	AMD Radeon R5 M320
-6667,	0,	AMD Radeon R5 M200 Series
-666F,	0,	AMD Radeon HD 8500M
-66A1,	06,	AMD Radeon Pro VII
-66AF,	C1,	AMD Radeon VII
-6780,	0,	ATI FirePro V (FireGL V) Graphics Adapter
-678A,	0,	ATI FirePro V (FireGL V) Graphics Adapter
-6798,	0,	AMD Radeon HD 7900 Series
-679A,	0,	AMD Radeon HD 7900 Series
-679B,	0,	AMD Radeon HD 7900 Series
-679E,	0,	AMD Radeon HD 7800 Series
-67A0,	0,	AMD Radeon FirePro W9100
-67A1,	0,	AMD Radeon FirePro W8100
-67B0,	0,	AMD Radeon R9 200 Series
-67B0,	80,	AMD Radeon R9 390 Series
-67B1,	0,	AMD Radeon R9 200 Series
-67B1,	80,	AMD Radeon R9 390 Series
-67B9,	0,	AMD Radeon R9 200 Series
-67DF,	C1,	AMD Radeon RX 580 Series
-67DF,	C2,	AMD Radeon RX 570 Series
-67DF,	C3,	AMD Radeon RX 580 Series
-67DF,	C4,	AMD Radeon RX 480 Graphics
-67DF,	C5,	AMD Radeon RX 470 Graphics
-67DF,	C6,	AMD Radeon RX 570 Series
-67DF,	C7,	AMD Radeon RX 480 Graphics
-67DF,	CF,	AMD Radeon RX 470 Graphics
-67DF,	D7,	AMD Radeon RX 470 Graphics
-67DF,	E0,	AMD Radeon RX 470 Series
-67DF,	E1,	AMD Radeon RX 590 Series
-67DF,	E3,	AMD Radeon RX Series
-67DF,	E7,	AMD Radeon RX 580 Series
-67DF,	EF,	AMD Radeon RX 570 Series
-67DF,	F7,	AMD Radeon RX P30PH
-67C2,	01,	AMD Radeon Pro V7350x2
-67C2,	02,	AMD Radeon Pro V7300X
-67C4,	00,	AMD Radeon Pro WX 7100 Graphics
-67C4,	80,	AMD Radeon E9560 / E9565 Graphics
-67C7,	00,	AMD Radeon Pro WX 5100 Graphics
-67C7,	80,	AMD Radeon E9390 Graphics
-67C0,	00,	AMD Radeon Pro WX 7100 Graphics
-67D0,	01,	AMD Radeon Pro V7350x2
-67D0,	02,	AMD Radeon Pro V7300X
-67E0,	00,	AMD Radeon Pro WX Series
-67E3,	00,	AMD Radeon Pro WX 4100
-67E8,	00,	AMD Radeon Pro WX Series
-67E8,	01,	AMD Radeon Pro WX Series
-67E8,	80,	AMD Radeon E9260 Graphics
-67EB,	00,	AMD Radeon Pro V5300X
-67EF,	C0,	AMD Radeon RX Graphics
-67EF,	C1,	AMD Radeon RX 460 Graphics
-67EF,	C3,	AMD Radeon RX Series
-67EF,	C5,	AMD Radeon RX 460 Graphics
-67EF,	C7,	AMD Radeon RX Graphics
-67EF,	CF,	AMD Radeon RX 460 Graphics
-67EF,	E2,	AMD Radeon RX 560X
-67EF,	E0,	AMD Radeon RX 560 Series
-67EF,	E1,	AMD Radeon RX Series
-67EF,	E3,	AMD Radeon RX Series
-67EF,	E5,	AMD Radeon RX 560 Series
-67EF,	EF,	AMD Radeon RX Graphics
-67EF,	FF,	AMD Radeon RX 460 Graphics
-67FF,	C0,	AMD Radeon RX Graphics
-67FF,	C1,	AMD Radeon RX Graphics
-67FF,	CF,	AMD Radeon RX 560 Series
-67FF,	EF,	AMD Radeon RX 560 Series
-67FF,	FF,	AMD Radeon RX 550 Series
-6800,	0,	AMD Radeon HD 7970M
-6801,	0,	AMD Radeon HD 8970M
-6808,	0,	ATI FirePro V(FireGL V) Graphics Adapter
-6809,	0,	ATI FirePro V(FireGL V) Graphics Adapter
-6810,	0,	AMD Radeon HD 8800 Series
-6810,	81,	AMD Radeon R7 370 Series
-6811,	0,	AMD Radeon HD 8800 Series
-6811,	81,	AMD Radeon R7 300 Series
-6818,	0,	AMD Radeon HD 7800 Series
-6819,	0,	AMD Radeon HD 7800 Series
-6820,	0,	AMD Radeon HD 8800M Series
-6820,	81,	AMD Radeon R9 M375
-6820,	83,	AMD Radeon R9 M375X
-6821,	0,	AMD Radeon HD 8800M Series
-6821,	87,	AMD Radeon R7 M380
-6821,	83,	AMD Radeon R9 M370X
-6822,	0,	AMD Radeon E8860
-6823,	0,	AMD Radeon HD 8800M Series
-6825,	0,	AMD Radeon HD 7800M Series
-6827,	0,	AMD Radeon HD 7800M Series
-6828,	0,	ATI FirePro V(FireGL V) Graphics Adapter
-682B,	0,	AMD Radeon HD 8800M Series
-682B,	87,	AMD Radeon R9 M360
-682C,	0,	AMD FirePro W4100
-682D,	0,	AMD Radeon HD 7700M Series
-682F,	0,	AMD Radeon HD 7700M Series
-6835,	0,	AMD Radeon R7 Series / HD 9000 Series
-6837,	0,	AMD Radeon HD 7700 Series
-683D,	0,	AMD Radeon HD 7700 Series
-683F,	0,	AMD Radeon HD 7700 Series
-6860,	00,	AMD Radeon Instinct MI25
-6860,	01,	AMD Radeon Instinct MI25
-6860,	02,	AMD Radeon Instinct MI25
-6860,	03,	AMD Radeon Pro V340
-6860,	04,	AMD Radeon Instinct MI25x2
-6860,	07,	AMD Radeon Pro V320
-6861,	00,	AMD Radeon Pro WX 9100
-6862,	00,	AMD Radeon Pro SSG
-6863,	00,	AMD Radeon Vega Frontier Edition
-6864,	03,	AMD Radeon Pro V340
-6864,	04,	AMD Radeon Instinct MI25x2
-6868,	00,	AMD Radeon Pro WX 8200
-686C,	00,	AMD Radeon Instinct MI25 MxGPU
-686C,	01,	AMD Radeon Instinct MI25 MxGPU
-686C,	02,	AMD Radeon Instinct MI25 MxGPU
-686C,	03,	AMD Radeon Pro V340 MxGPU
-686C,	04,	AMD Radeon Instinct MI25x2 MxGPU
-686C,	05,	AMD Radeon Pro V340L MxGPU
-686C,	06,	AMD Radeon Instinct MI25 MxGPU
-687F,	C0,	AMD Radeon RX Vega
-687F,	C1,	AMD Radeon RX Vega
-687F,	C3,	AMD Radeon RX Vega
-6900,	0,	AMD Radeon R7 M260
-6900,	81,	AMD Radeon R7 M360
-6900,	83,	AMD Radeon R7 M340
-6901,	0,	AMD Radeon R5 M255
-6907,	0,	AMD Radeon R5 M255
-6907,	87,	AMD Radeon R5 M315
-6920,	0,	AMD Radeon R9 M395X
-6920,	1,	AMD Radeon R9 M390X
-6921,	0,	AMD Radeon R9 M295X
-6929,	0,	AMD FirePro S7150
-692B,	0,	AMD FirePro W7100
-6938,	0,	AMD Radeon R9 200 Series
-6938,	F0,	AMD Radeon R9 200 Series
-6938,	F1,	AMD Radeon R9 380 Series
-6939,	F0,	AMD Radeon R9 200 Series
-6939,	0,	AMD Radeon R9 200 Series
-6939,	F1,	AMD Radeon R9 380 Series
-6980,	00,	AMD Radeon Pro WX 3100
-6981,	00,	AMD Radeon Pro WX 3200 Series
-6981,	01,	AMD Radeon Pro WX 3200 Series
-6981,	10,	AMD Radeon Pro WX 3200 Series
-6985,	00,	AMD Radeon Pro WX 3100
-6987,	80,	AMD Embedded Radeon E9171
-6987,	C0,	AMD Radeon 550X Series
-6987,	C1,	AMD Radeon RX 640
-6987,	C3,	AMD Radeon 540X Series
-6995,	00,	AMD Radeon Pro WX 2100
-6997,	00,	AMD Radeon Pro WX 2100
-699F,	81,	AMD Embedded Radeon E9170 Series
-699F,	C0,	AMD Radeon 500 Series
-699F,	C1,	AMD Radeon 540 Series
-699F,	C3,	AMD Radeon 500 Series
-699F,	C7,	AMD Radeon RX 550 / 550 Series
-7300,	C1,	AMD FirePro S9300 x2
-7300,	C8,	AMD Radeon R9 Fury Series
-7300,	C9,	AMD Radeon Pro Duo
-7300,	CB,	AMD Radeon R9 Fury Series
-7300,	CA,	AMD Radeon R9 Fury Series
-7312,	00,	AMD Radeon Pro W5700
-731E,	C6,	AMD Radeon RX 5700XTB
-731E,	C7,	AMD Radeon RX 5700B
-731F,	C0,	AMD Radeon RX 5700 XT 50th Anniversary
-731F,	C1,	AMD Radeon RX 5700 XT
-731F,	C2,	AMD Radeon RX 5600M
-731F,	C3,	AMD Radeon RX 5700M
-731F,	C4,	AMD Radeon RX 5700
-731F,	C5,	AMD Radeon RX 5700 XT
-731F,	CA,	AMD Radeon RX 5600 XT
-731F,	CB,	AMD Radeon RX 5600 OEM
-7340,	C1,	AMD Radeon RX 5500M
-7340,	C5,	AMD Radeon RX 5500 XT
-7340,	C7,	AMD Radeon RX 5500
-7340,	C9,	AMD Radeon RX 5500XTB
-7340,	CF,	AMD Radeon RX 5300
-7341,	00,	AMD Radeon Pro W5500
-7347,	00,	AMD Radeon Pro W5500M
-73A3,	00,	AMD Radeon Pro W6800
-73AF,	C0,	AMD Radeon RX 6900 XT
-73BF,	C0,	AMD Radeon RX 6900 XT
-73BF,	C1,	AMD Radeon RX 6800 XT
-73BF,	C3,	AMD Radeon RX 6800
-73DF,	C1,	AMD Radeon RX 6700 XT
-73DF,	C3,	AMD Radeon RX 6800M
-73DF,	C5,	AMD Radeon RX 6700 XT
-73DF,	CF,	AMD Radeon RX 6700M
-73E1,	00,	AMD Radeon Pro W6600M
-73E3,	00,	AMD Radeon Pro W6600
-73FF,	C1,	AMD Radeon RX 6600 XT
-73FF,	C3,	AMD Radeon RX 6600M
-9874,	C4,	AMD Radeon R7 Graphics
-9874,	C5,	AMD Radeon R6 Graphics
-9874,	C6,	AMD Radeon R6 Graphics
-9874,	C7,	AMD Radeon R5 Graphics
-9874,	C8,	AMD Radeon R7 Graphics
-9874,	81,	AMD Radeon R6 Graphics
-9874,	87,	AMD Radeon R5 Graphics
-9874,	85,	AMD Radeon R6 Graphics
-9874,	84,	AMD Radeon R7 Graphics
-6FDF,	E7,	AMD Radeon RX 590 GME
-6FDF,	EF,	AMD Radeon RX 580 2048SP
diff --git a/prebuilts/x86_64/share/libdrm/amdgpu.ids b/prebuilts/x86_64/share/libdrm/amdgpu.ids
index 0040a38..0d2b884 100644
--- a/prebuilts/x86_64/share/libdrm/amdgpu.ids
+++ b/prebuilts/x86_64/share/libdrm/amdgpu.ids
@@ -275,18 +275,35 @@
 7341,	00,	AMD Radeon Pro W5500
 7347,	00,	AMD Radeon Pro W5500M
 73A3,	00,	AMD Radeon Pro W6800
+73A5,	C0,	AMD Radeon RX 6950 XT
 73AF,	C0,	AMD Radeon RX 6900 XT
 73BF,	C0,	AMD Radeon RX 6900 XT
 73BF,	C1,	AMD Radeon RX 6800 XT
 73BF,	C3,	AMD Radeon RX 6800
+73DF,	C0,	AMD Radeon RX 6750 XT
 73DF,	C1,	AMD Radeon RX 6700 XT
 73DF,	C3,	AMD Radeon RX 6800M
 73DF,	C5,	AMD Radeon RX 6700 XT
 73DF,	CF,	AMD Radeon RX 6700M
 73E1,	00,	AMD Radeon Pro W6600M
 73E3,	00,	AMD Radeon Pro W6600
+73EF,	C0,	AMD Radeon RX 6800S
+73EF,	C1,	AMD Radeon RX 6650 XT
+73EF,	C2,	AMD Radeon RX 6700S
+73EF,	C3,	AMD Radeon RX 6650M
+73EF,	C4,	AMD Radeon RX 6650M XT
 73FF,	C1,	AMD Radeon RX 6600 XT
 73FF,	C3,	AMD Radeon RX 6600M
+73FF,	C7,	AMD Radeon RX 6600
+73FF,	CB,	AMD Radeon RX 6600S
+7421,	00,	AMD Radeon Pro W6500M
+7422,	00,	AMD Radeon PRO W6400
+7423,	00,	AMD Radeon Pro W6300M
+7424,	00,	AMD Radeon RX 6300
+743F,	C1,	AMD Radeon RX 6500 XT
+743F,	C3,	AMD Radeon RX 6500
+743F,	C7,	AMD Radeon RX 6400
+743F,	CF,	AMD Radeon RX 6300M
 9874,	C4,	AMD Radeon R7 Graphics
 9874,	C5,	AMD Radeon R6 Graphics
 9874,	C6,	AMD Radeon R6 Graphics